Upstream cmsis harpoon v2.4 #272
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Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The header file only to resolve aarch64 compatible issue for CMSIS header files and drivers. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Support ca53 Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit ee9a1452a2a95cf07b43a0892475675f86f12259) [Only c-pick core_ca53.h and update commit title] Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Eventually, gic_v3.h will be included by other SoC, such as other Cortex-A5x. Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
GNU GCC (AS) is not aware of all Aarch64 symbolic system registers names. Fetch their definitions from the ARM documentation (instruction encoding from register descriptions). Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Ths current parameter (mainCore) is unused ; instead of imposing core 0 as the main code, let the caller decide what core shall initialize the GIC Distributor. Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Use it to access ->WAKER field. Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Zephyr has its own implementation of __ISB() and friends ; let's not redefine them if already defined. This _workaround_ consists in defining the macros only if they are not defined yet. Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
We usually pass a pointer to a variable to get value ; let's do this with the __MRS() macro as well. Suggested-by: Rui Sousa <rui.sousa@nxp.com> Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
TODO: Remove dependency on this file by inserting MSR/MRS instructions directly in the source code. Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
The MMU config is best known by the application iteself, depending on the SoC, RTOS and use case being executed. Let the MMU intialization API function take the config as a paramter for a better flexibility. Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Define __NOP() function for Cortext A CMSIS. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Reported-by: Jiafei Pan <Jiafei.Pan@nxp.com> Suggested-by: Fabrice Goucem <fabrice.goucem@nxp.com> Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Add function to set a new individual MMU map at run-time. Signed-off-by: Rui Sousa <rui.sousa@nxp.com>
Increase the number of MMU translation tables. For the audio application with ivshmem support, the current limit was being reached. Signed-off-by: Rui Sousa <rui.sousa@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Add API to get timer counter value. Signed-off-by: Rui Sousa <rui.sousa@nxp.com>
The current ARM_TIMER API's Start and EnableIRQ are not working as expected: - Start always enables IRQ's - EnableIRQ always disables the timer Fix by removing the standalone EnableIRQ API and adding an irq enable flag to Start API. Signed-off-by: Rui Sousa <rui.sousa@nxp.com>
Add compiler abstraction for weak linkage (__WEAK macro) Signed-off-by: Rui Sousa <rui.sousa@nxp.com>
The counter-timer Frequency register is common to all types of counters. There is no need to pass the type of timer in parameter. Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
…he tracked registers Add polling of RWP bit of Distributor and Redistributor CTRL registers to make sure the effects of previous register writes to the affected register fields are visible to all logical components of the GIC architecture. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
…PI interrupt Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
In the case of using an hypervisor, we should not setup the affinity to a specific CPU, as it depends on the CPU used for the guest OS. Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
…TOS security extension In some cases, the lower half of available priorities values are reserved by the OS for critical functions, as part of the legacy security extension feature (for example in FreeRTOS). By using 2/3 of the max priority of the GIC, we ensure that we have a valid default value. Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
And add MPIDR_EL1 affinity fields mask definition. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The MT bit of MPIDR_EL indicates if Affinity0 is Thread ID, if MT is set, the Affinity1 is Core ID. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Change the 'target_core' arguement to 64bit to fully initialize the 64bit IROUTER register. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Return the full Affinity field when Affinity routing is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
In the processors, which integrates the multi-threaded cores, the definition of the affinity fields in MPIDR_EL1 is different, the Affinity0 is used to indicate Thread ID instead of Core ID. However, the current implementation hard-code to use Affinity0 to identify Core ID and then index the Redistributor, so it does't work anymore on these platforms. This patch remove the hard-code indenification of Redistributor and change to use the core/thread's affinity fields to match the Redistributor. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To mark the connected PE as being online, software must: - Clear GICR_WAKER.ProcessorSleep to 0. - Poll GICR_WAKER.ChildrenAsleep until it reads 0. It is important that software performs these steps before configuring the CPU interface, otherwise behavior can be UNPREDICTABLE. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Refine the CPU interface initialization sequence according to the GIC CPU interface configration guide. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
And Core header file for Cortex-A55 Core. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Includes the AArch64 common header file to avoid duplicate code. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
In general, group0 is used by secure el3, so use non-secure group1 for all SPI interrupts. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Merged
The KB define is unnecessarily polluting the namespace (clashes with zephyr/sys/util.h definition) since it is only used once in a source file. To fix the problem, definition has been moved to the source file. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> Rebased to Core_AArch64. Signed-off-by: Jiafei Pan <jiafei.pan@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
mmahadevan108
approved these changes
Sep 13, 2023
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Port CMSIS update for Harpoon v2.4 from https://github.com/nxp-mcuxpresso/CMSIS_5/commits/mcux_develop, commit from 9040b83fabf32dc0be32dced673439b4a9136294 to 66a180f8b67fb3fdd11271bb31f5abec42fa2f62