LoongArch: update ABI-related builtin macros. (gcc-mirror#49)

Co-authored-by: Yang Yujie <yangyujie@loongson.cn>

gcc/config/loongarch/loongarch-c.c

@@ -64,42 +64,54 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
   builtin_assert ("cpu=loongarch");
   builtin_define ("__loongarch__");
 
-  if (TARGET_FLOAT64)
-    builtin_define ("__loongarch_fpr=64");
-  else
-    builtin_define ("__loongarch_fpr=32");
-
   LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_ARCH", loongarch_cpu_arch);
   LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_TUNE", loongarch_cpu_tune);
 
+  /* Integer ISA/ABI */
+  if (TARGET_64BIT)
+    builtin_define ("__loongarch_gpr=64");
+
   switch (loongarch_abi_int)
     {
     case ABI_LP64:
       builtin_define ("_ABILP64=3");
       builtin_define ("_LOONGARCH_SIM=_ABILP64");
       builtin_define ("__loongarch64");
+      builtin_define ("__loongarch_lp64");
       break;
     }
 
-  builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE);
-  builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE);
-  builtin_define_with_int_value ("_LOONGARCH_SZPTR", POINTER_SIZE);
-  builtin_define_with_int_value ("_LOONGARCH_FPSET", 32 / MAX_FPRS_PER_FMT);
-  builtin_define_with_int_value ("_LOONGARCH_SPFPSET", 32);
+  /* Floating-Point ISA/ABI */
+  if (TARGET_DOUBLE_FLOAT)
+    builtin_define ("__loongarch_fpr=64");
+  else if (TARGET_SINGLE_FLOAT)
+    builtin_define ("__loongarch_fpr=32");
+  else
+    builtin_define ("__loongarch_fpr=0");
 
   /* These defines reflect the ABI in use, not whether the
      FPU is directly accessible.  */
-  if (TARGET_HARD_FLOAT_ABI)
+  if (TARGET_DOUBLE_FLOAT_ABI)
+    builtin_define ("__loongarch_double_float");
+  else if (TARGET_SINGLE_FLOAT_ABI)
+    builtin_define ("__loongarch_single_float");
+
+  if (TARGET_DOUBLE_FLOAT_ABI || TARGET_SINGLE_FLOAT_ABI)
     builtin_define ("__loongarch_hard_float");
   else
     builtin_define ("__loongarch_soft_float");
 
-  if (TARGET_SINGLE_FLOAT)
-    builtin_define ("__loongarch_single_float");
-
+  /* ISA Extensions / Features */
   if (TARGET_FIX_LOONGSON3_LLSC)
     builtin_define ("__fix_loongson3_llsc");
 
+  /* Native Data Sizes */
+  builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_SZPTR", POINTER_SIZE);
+  builtin_define_with_int_value ("_LOONGARCH_FPSET", 32 / MAX_FPRS_PER_FMT);
+  builtin_define_with_int_value ("_LOONGARCH_SPFPSET", 32);
+
   /* Macros dependent on the C dialect.  */
   if (preprocessing_asm_p ())
     {

gcc/config/loongarch/loongarch-opts.h

@@ -116,14 +116,15 @@ loongarch_handle_m_option_combinations (
 
 
 /* Legacy conditional expression macros (TODO: cleanup) */
-#define TARGET_HARD_FLOAT      (loongarch_isa_float != ISA_SOFT_FLOAT)
-#define TARGET_HARD_FLOAT_ABI  (loongarch_abi_float != ABI_SOFT_FLOAT)
-#define TARGET_SOFT_FLOAT      (loongarch_isa_float == ISA_SOFT_FLOAT)
-#define TARGET_SOFT_FLOAT_ABI  (loongarch_abi_float == ABI_SOFT_FLOAT)
-#define TARGET_SINGLE_FLOAT    (loongarch_abi_float == ABI_SINGLE_FLOAT)
-#define TARGET_DOUBLE_FLOAT    (loongarch_abi_float == ABI_DOUBLE_FLOAT)
-#define TARGET_FLOAT64         \
-  (loongarch_isa_float == ISA_DOUBLE_FLOAT || loongarch_isa_float == ISA_SOFT_FLOAT)
+#define TARGET_HARD_FLOAT        (loongarch_isa_float != ISA_SOFT_FLOAT)
+#define TARGET_HARD_FLOAT_ABI    (loongarch_abi_float != ABI_SOFT_FLOAT)
+#define TARGET_SOFT_FLOAT        (loongarch_isa_float == ISA_SOFT_FLOAT)
+#define TARGET_SOFT_FLOAT_ABI    (loongarch_abi_float == ABI_SOFT_FLOAT)
+#define TARGET_SINGLE_FLOAT      (loongarch_isa_float == ISA_SINGLE_FLOAT)
+#define TARGET_SINGLE_FLOAT_ABI  (loongarch_abi_float == ABI_SINGLE_FLOAT)
+#define TARGET_DOUBLE_FLOAT      (loongarch_isa_float == ISA_DOUBLE_FLOAT)
+#define TARGET_DOUBLE_FLOAT_ABI  (loongarch_abi_float == ABI_DOUBLE_FLOAT)
+
 #define TARGET_ABI_LP64        (loongarch_abi_int == ABI_LP64)
 #define TARGET_64BIT           (loongarch_isa_int == ISA_LA64)
 

gcc/config/loongarch/loongarch.h

@@ -209,11 +209,11 @@ along with GCC; see the file COPYING3.  If not see
 #endif
 
 /* For LARCH, width of a floating point register.  */
-#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
+#define UNITS_PER_FPREG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 
 /* The number of consecutive floating-point registers needed to store the
    largest format supported by the FPU.  */
-#define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
+#define MAX_FPRS_PER_FMT 1
 
 /* The number of consecutive floating-point registers needed to store the
    smallest format supported by the FPU.  */
@@ -222,12 +222,12 @@ along with GCC; see the file COPYING3.  If not see
 /* The largest size of value that can be held in floating-point
    registers and moved with a single instruction.  */
 #define UNITS_PER_HWFPVALUE \
-  (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
+  (TARGET_SOFT_FLOAT ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
 
 /* The largest size of value that can be held in floating-point
    registers.  */
 #define UNITS_PER_FPVALUE \
-  (TARGET_SOFT_FLOAT_ABI ? 0 \
+  (TARGET_SOFT_FLOAT ? 0 \
    : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
 			 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
 
@@ -1320,6 +1320,6 @@ struct GTY (()) machine_function
 
 /* The largest type that can be passed in floating-point registers.  */
 /* TODO: according to mabi.  */
-#define UNITS_PER_FP_ARG (TARGET_HARD_FLOAT ? (TARGET_64BIT ? 8 : 4) : 0)
+#define UNITS_PER_FP_ARG (TARGET_HARD_FLOAT ? (TARGET_DOUBLE_FLOAT ? 8 : 4) : 0)
 
 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)

gcc/config/loongarch/loongarch.md

@@ -418,8 +418,7 @@
 (define_mode_iterator JOIN_MODE [HI
 				 SI
 				 (SF "TARGET_HARD_FLOAT")
-				 (DF "TARGET_HARD_FLOAT
-				      && TARGET_DOUBLE_FLOAT")])
+				 (DF "TARGET_DOUBLE_FLOAT")])
 
 ;; This mode iterator allows :P to be used for patterns that operate on
 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
@@ -442,13 +441,13 @@
 
 ;; Iterator for hardware-supported floating-point modes.
 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
-			    (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
+			    (DF "TARGET_DOUBLE_FLOAT")])
 
 ;; A floating-point mode for which moves involving FPRs may need to be split.
 (define_mode_iterator SPLITF
   [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
    (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
-   (TF "TARGET_64BIT && TARGET_FLOAT64")])
+   (TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")])
 
 ;; In GPR templates, a string like "mul.<d>" will expand to "mul" in the
 ;; 32-bit "mul.w" and "mul.d" in the 64-bit version.
@@ -1258,7 +1257,7 @@
 (define_insn "truncdfsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
   "fcvt.s.d\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "cnv_mode"	"D2S")
@@ -1520,7 +1519,7 @@
 (define_insn "extendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
   "fcvt.d.s\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "cnv_mode"	"S2D")
@@ -1538,7 +1537,7 @@
 (define_insn "fix_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
 	(fix:SI (match_operand:DF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
   "ftintrz.w.d %0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")
@@ -1557,7 +1556,7 @@
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
 	(fix:DI (match_operand:DF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
   "ftintrz.l.d %0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")
@@ -1567,7 +1566,7 @@
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
 	(fix:DI (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
   "ftintrz.l.s %0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"SF")
@@ -1578,7 +1577,7 @@
 (define_insn "floatsidf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(float:DF (match_operand:SI 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
   "ffint.d.w\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")
@@ -1588,7 +1587,7 @@
 (define_insn "floatdidf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(float:DF (match_operand:DI 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
   "ffint.d.l\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")
@@ -1608,7 +1607,7 @@
 (define_insn "floatdisf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float:SF (match_operand:DI 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
   "ffint.s.l\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"SF")
@@ -1619,7 +1618,7 @@
 (define_expand "fixuns_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand")
 	(unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
 {
   rtx reg1 = gen_reg_rtx (DFmode);
   rtx reg2 = gen_reg_rtx (DFmode);
@@ -1665,7 +1664,7 @@
 (define_expand "fixuns_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand")
 	(unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
-  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
 {
   rtx reg1 = gen_reg_rtx (DFmode);
   rtx reg2 = gen_reg_rtx (DFmode);
@@ -1749,7 +1748,7 @@
 (define_expand "fixuns_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand")
 	(unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
-  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT"
 {
   rtx reg1 = gen_reg_rtx (SFmode);
   rtx reg2 = gen_reg_rtx (SFmode);
@@ -2021,7 +2020,7 @@
 (define_insn "*movdf_hardfloat"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*r,*r,*r,*m")
 	(match_operand:DF 1 "move_operand" "f,G,m,f,G,*r,*f,*r*G,*m,*r"))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+  "TARGET_DOUBLE_FLOAT
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return loongarch_output_move (operands[0], operands[1]); }
@@ -2410,7 +2409,7 @@
 	(unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "rJ")
 			(match_operand:SPLITF 2 "register_operand" "0")]
 			UNSPEC_MOVGR2FRH))]
-  "TARGET_HARD_FLOAT && TARGET_FLOAT64"
+  "TARGET_DOUBLE_FLOAT"
   "movgr2frh.w\t%z1,%0"
   [(set_attr "move_type" "mgtf")
    (set_attr "mode" "<HALFMODE>")])
@@ -2420,7 +2419,7 @@
   [(set (match_operand:<HALFMODE> 0 "register_operand" "=r")
 	(unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
 			    UNSPEC_MOVFRH2GR))]
-  "TARGET_HARD_FLOAT && TARGET_FLOAT64"
+  "TARGET_DOUBLE_FLOAT"
   "movfrh2gr.s\t%0,%1"
   [(set_attr "move_type" "mftg")
    (set_attr "mode" "<HALFMODE>")])