Skip to content
View vicky089f's full-sized avatar

Block or report vicky089f

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
vicky089f/README.md
  • 👋 Hi, I’m Vignesh Bharadwaj
  • 👀 I’m interested in digital logic design, RTL design, computer architecture and digital VLSI design
  • 🌱 I’m currently working in the VLSI industry
  • 📫 You can reach me through my email: vicky089f@gmail.com or message me on linkedin: Vingesh Bharadwaj

Popular repositories Loading

  1. IITH_Hackathon_Approximate_Multiplier IITH_Hackathon_Approximate_Multiplier Public

    Dadda multiplier using half adders, full adders, and approximate 4:2 compressors

    2

  2. RV32I RV32I Public

    Implementation of the 5-stage pipelined processor based on the RV32I ISA

    Verilog 2

  3. 8_bit_Processor 8_bit_Processor Public

    Implementation of a simple 8-bit processor in Verilog

    Verilog 1

  4. Instruction_Cache Instruction_Cache Public

    A simple instruction cache model in verilog

    Verilog 1

  5. Assembler_RV32I Assembler_RV32I Public

    An assembler written in python for the RV32I instruction set

    Python 1

  6. eSim_Marathon_6T_SRAM eSim_Marathon_6T_SRAM Public

    Circuit Design and Simulation Marathon using eSim

    1