[WIP] Synlig, new system-verilog tool integration #2841

amirarjmand93 · 2024-12-08T15:26:36Z

Description

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Motivation and Context

How Has This Been Tested?

Types of changes

Bug fix (change which fixes an issue)
New feature (change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

My change requires a change to the documentation
I have updated the documentation accordingly
I have added tests to cover my changes
All new and existing tests passed

…mys + paths updated]

amirarjmand93 · 2024-12-08T20:50:01Z

@vaughnbetz This branch is working on the local pc fine without any problem. but in the CI test, I am getting some errors related to JAVA dependency while making files. for Synlig we need some packages to be installed:

apt install -y gcc-11 g++-11 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev python3-pip uuid uuid-dev tcl-dev flex libfl-dev git pkg-config libreadline-dev bison libffi-dev wget python3-orderedmultidict

I tried to append some packages from this list that are missing from our flow. (like default-jre). I added them to the .github folder inside three bash files(in the figure) but I think I should add them in other files also.

This error arises from most of the ci tests:

vaughnbetz · 2024-12-09T02:14:45Z

@AlexandreSinger @soheilshahrouz : any ideas?

amirarjmand93 · 2024-12-11T16:07:18Z

why hasn't the nightly test been launched?

vaughnbetz · 2024-12-12T00:19:06Z

We had to turn off automatic launch of the nightly tests as we don't have the google cloud going. You should run some or all of the nightly tests manually if this code change could break them. @AlexandreSinger : not sure if you have a button that can launch the nightly tests on one of our SAVI servers or not yet.

amirarjmand93 · 2024-12-16T05:49:01Z

1- vtr_reg_system_verilog.log.txt
2- parmys_reg_strong.log.txt

The two tests from the nightly tests related to SystemVerilog were run successfully with Synlig enabled(cmake: -DYOSYS_F4PGA_PLUGINS=ON) during the make process. Other nightly tests generate VTR while Synlig (formerly known as cmake: -DYOSYS_F4PGA_PLUGINS) is disabled(OFF), and there should be no issues with the new integration.

vaughnbetz

Thanks for handling this! I have some suggested changes to reduce code duplication and clarify some messages/comments.

vaughnbetz · 2024-12-16T18:21:38Z

vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py

@@ -0,0 +1,65 @@
+"""


It seems like you have 3 copies of the make_sv_flattened.py script. Why not put it in the base f4pga directory instead and just call it from there (with ../../make_sv_flattened.py)? Or put it in the search path.

vaughnbetz · 2024-12-16T18:22:46Z

vtr_flow/misc/yosys/synthesis.tcl

+
+# Separate opt for Parmys execution(verilog or system-verilog)
+if {$env(PARSER) == "default"} {
+    puts "Running Parmys with disables additional passes "


I'm not sure what this output means. Do you mean to say "Running parmys with no additional passes." ?

vaughnbetz · 2024-12-16T18:23:42Z

vtr_flow/misc/yosys/synthesis.tcl

+    parmys -a QQQ -nopass -c CCC YYY
+
+} elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} {
+    puts "Running Parmys with Additional Passes Resolve Conflicts"


I'm not sure what this output means. Wouldn't it be more clear to say "Running Parmys with additional passes to flatten all files and parse SystemVerilog" ?

vaughnbetz · 2024-12-16T18:26:03Z

.github/workflows/nightly_test.yml

@@ -65,9 +65,9 @@ jobs:
          - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
          - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
          - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          # - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
+          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)


The comment looks out of date -- it says this test is turned off, but you are turning it back on. Delete the comment.
Also is synlig part of f4pga_plugins? If not, it would be better to change the name of the cmake variable to synlig for clarity.

amirarjmand93 · 2024-12-16T18:49:45Z

I am aware of these comments and duplicates. I just want to ensure that we are technically finished with this update and the last commits. I will make the minor changes and let you know.

vaughnbetz · 2025-01-21T03:35:54Z

Thanks! Do we have one copy of make_sv_flattened.py somewhere still? Or is it no longer needed? (It seems all 3 copies added in this PR have now been deleted).

vaughnbetz

Thanks for adding that back in. I'm not sure what our submodule update policy is for things like sockpp (not sure if we're trying to stay on a specific commit or not) ... it looks fine to me to update that submodule and catch2 but pinging @AlexandreSinger in case he has any thoughts.

AlexandreSinger · 2025-01-21T14:46:02Z

@vaughnbetz SockPP is on a special branch made by Oleksander which resolves some warnings that were in the library. We need those changes to be warning clean (and pass CI). This is what, I think, is causing the CI to currently fail for this PR:

Catch2 does not have this issue, and we just follow whatever the most recent version is.

vaughnbetz · 2025-01-21T23:09:43Z

@amirarjmand93 : please revert the two submodule updates. The sockpp one is making CI fail the warning tests. I'm not sure if the libcatch one moved us to an older version or not and it doesn't seem to be causing problems, but since it is not an intended update for this PR I'd rather be safe and limit this PR to the code necessary to bring SV support back.

synlig, new system verilog tool integration [build system + tcl + par…

ec618c0

…mys + paths updated]

github-actions bot added infra Project Infrastructure lang-python Python code lang-make CMake/Make code external_libs labels Dec 8, 2024

synlig, new system verilog tool integration [build system + tcl + par…

f2eca1a

…mys + paths updated]

github-actions bot added the lang-shell Shell scripts (bash etc.) label Dec 8, 2024

amirarjmand93 changed the title ~~synlig, new system verilog tool integration~~ synlig, new system-verilog tool integration Dec 8, 2024

amirarjmand93 changed the title ~~synlig, new system-verilog tool integration~~ Synlig, new system-verilog tool integration Dec 8, 2024

github-actions bot added the scripts Utility & Infrastructure scripts label Dec 9, 2024

parmys file error handling

7e4632f

amirarjmand93 force-pushed the vtr+synlig branch from 6cf731f to 7e4632f Compare December 9, 2024 23:40

amirarjmand93 added 10 commits December 9, 2024 21:24

minor update

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minor update

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minor update

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minor update

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minor update

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minor update

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minor update

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turn on sv test

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turn on sv test

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tcl update - error handling

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amirarjmand93 changed the title ~~Synlig, new system-verilog tool integration~~ [WIP] Synlig, new system-verilog tool integration Dec 10, 2024

f4pga systemverilog tests flattened

ff6dd80

github-actions bot added the lang-hdl Hardware Description Language (Verilog/VHDL) label Dec 16, 2024

lint error solved

bddc654

lint error solved

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vaughnbetz requested changes Dec 16, 2024

View reviewed changes

amirarjmand93 added 2 commits January 20, 2025 22:36

Update documentation to reflect migration from F4PGA to Synlig

ef73d0e

Merge branch 'master' into vtr+synlig

e04a11e

github-actions bot added docs Documentation build Build system labels Jan 21, 2025

add missed make_sv_flattened.py

7659c08

vaughnbetz reviewed Jan 21, 2025

View reviewed changes

Merge branch 'master' into vtr+synlig

64b289b

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[WIP] Synlig, new system-verilog tool integration #2841

[WIP] Synlig, new system-verilog tool integration #2841

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[WIP] Synlig, new system-verilog tool integration #2841

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[WIP] Synlig, new system-verilog tool integration #2841

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amirarjmand93 commented Dec 8, 2024 • edited Loading

Description

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

Checklist:

amirarjmand93 commented Dec 8, 2024

vaughnbetz commented Dec 9, 2024

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