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[WIP] Yosys v42 + f4pga off #2642

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wants to merge 23 commits into from
Closed

[WIP] Yosys v42 + f4pga off #2642

wants to merge 23 commits into from

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amirarjmand93
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@amirarjmand93 amirarjmand93 commented Jul 8, 2024 •
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Description

retrieve parmys_reg_strong . make with "-DYOSYS_F4PGA_PLUGINS=OFF"

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@github-actions github-actions bot added the infra Project Infrastructure label Jul 8, 2024
@amirarjmand93 amirarjmand93 changed the title pending test -> retrieve parmys_reg_strong [WIP] pending test -> retrieve parmys_reg_strong Jul 8, 2024
@github-actions github-actions bot added lang-cpp C/C++ code lang-python Python code lang-make CMake/Make code lang-hdl Hardware Description Language (Verilog/VHDL) lang-shell Shell scripts (bash etc.) Parmys labels Jul 9, 2024
@amirarjmand93 amirarjmand93 changed the title [WIP] pending test -> retrieve parmys_reg_strong [WIP] Yosys v42 + f4pga off Jul 9, 2024
@amirarjmand93 amirarjmand93 mentioned this pull request Jul 10, 2024
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@amirarjmand93 amirarjmand93 changed the title [WIP] Yosys v42 + f4pga off Yosys v42 + f4pga off Jul 15, 2024
@amirarjmand93 amirarjmand93 changed the title Yosys v42 + f4pga off [WIP] Yosys v42 + f4pga off Jul 15, 2024
@amirarjmand93 amirarjmand93 reopened this Jul 15, 2024
@amirarjmand93 amirarjmand93 deleted the f4pga_off_test branch August 7, 2024 14:37
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infra Project Infrastructure lang-cpp C/C++ code lang-hdl Hardware Description Language (Verilog/VHDL) lang-make CMake/Make code lang-python Python code lang-shell Shell scripts (bash etc.) libvtrutil Parmys
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