lint error solved

verilog-to-routing · Dec 16, 2024 · bddc654 · bddc654
1 parent ff6dd80
commit bddc654
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diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py
diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/make_sv_flattened.py b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/make_sv_flattened.py
@@ -1,3 +1,7 @@
+"""
+Module for flattening the SV design files.
+"""
+
 import os
 import re
 

diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py b/vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py
@@ -1,3 +1,7 @@
+"""
+Module for flattening the SV design files.
+"""
+
 import os
 import re