fix: S-interpolator for assert, assume and printf

src/test/scala/chiseltest/backends/icarus/IcarusBlackBoxTest.scala

@@ -55,7 +55,8 @@ class PlusArgReader extends BlackBox with HasBlackBoxInline {
 
 class PlusArgReaderWrapper(expected: Int) extends Module {
   val reader = Module(new PlusArgReader)
-  assert(reader.io.out === expected.U, s"Expected $expected, got %x.\n", reader.io.out)
+  val msg = s"Expected $expected, got %x.\n" // this works around the fact that s".." is forbidden in the assert
+  assert(reader.io.out === expected.U, msg, reader.io.out)
 }
 
 class IcarusBlackBoxTests extends AnyFlatSpec with ChiselScalatestTester {

src/test/scala/chiseltest/backends/treadle/TreadleBlackBoxTest.scala

@@ -45,7 +45,8 @@ class PlusArgReaderTreadleImpl extends ScalaBlackBoxFactory with ScalaBlackBox {
 
 class PlusArgReaderWrapper(expected: Int) extends Module {
   val reader = Module(new PlusArgReader)
-  assert(reader.io.out === expected.U, s"Expected $expected, got %x.\n", reader.io.out)
+  val msg = s"Expected $expected, got %x.\n" // this works around the fact that s".." is forbidden in the assert
+  assert(reader.io.out === expected.U, msg, reader.io.out)
 }
 
 class TreadleBlackBoxTest extends AnyFlatSpec with ChiselScalatestTester {

src/test/scala/chiseltest/backends/verilator/VerilogBlackBoxTest.scala

@@ -55,7 +55,8 @@ class PlusArgReader extends BlackBox with HasBlackBoxInline {
 
 class PlusArgReaderWrapper(expected: Int) extends Module {
   val reader = Module(new PlusArgReader)
-  assert(reader.io.out === expected.U, s"Expected $expected, got %x.\n", reader.io.out)
+  val msg = s"Expected $expected, got %x.\n" // this works around the fact that s".." is forbidden in the assert
+  assert(reader.io.out === expected.U, msg, reader.io.out)
 }
 
 class VerilogBlackBoxTests extends AnyFlatSpec with ChiselScalatestTester {

src/test/scala/chiseltest/formal/ExpressionSemanticsTests.scala

@@ -24,8 +24,10 @@ class DivisionVsShiftTest extends Module {
   assert(numerator / 1.U === numerator)
   val powers = Seq.tabulate(10)(ii => (ii, BigInt(1) << ii))
   powers.foreach { case (ii, pow) =>
-    assert(numerator / pow.U === (numerator >> ii.U), s"num / $pow == num >> $ii")
-    assert(numerator / pow.U === numerator.head(width - ii), s"num / $pow == num[${width-1}:$ii]")
+    val msg1 = s"num / $pow == num >> $ii" // this works around the fact that s".." is forbidden in the assert
+    assert(numerator / pow.U === (numerator >> ii.U), msg1)
+    val msg2 = s"num / $pow == num[${width-1}:$ii]" // this works around the fact that s".." is forbidden in the assert
+    assert(numerator / pow.U === numerator.head(width - ii), msg2)
   }
 }
 
@@ -72,8 +74,10 @@ class DivisionAndRemainderTest(oracle: DivisionAndRemainderOracle) extends Modul
     val div = oracle.div(num, den)
     val rem = oracle.rem(num, den)
     val div_res = (num.U / den.U).suggestName(s"${num}_div_${den}_res")
-    assert(div_res === div.U, s"$num / $den == $div")
+    val msg1 = s"$num / $den == $div" // this works around the fact that s".." is forbidden in the assert
+    assert(div_res === div.U, msg1)
     val rem_res = (num.U % den.U).suggestName(s"${num}_rem_${den}_res")
-    assert(rem_res === rem.U, s"$num %% $den == $rem")
+    val msg2 = s"$num %% $den == $rem" // this works around the fact that s".." is forbidden in the assert
+    assert(rem_res === rem.U, msg2)
   }
-}
+}

src/test/scala/chiseltest/iotesters/examples/FixedIsWholeTester.scala

@@ -21,7 +21,7 @@ class FixedIsWhole(w: Int) extends Module {
   val lsbsChopped = io.in.setBinaryPoint(0)
   val lsbsZeroed = (lsbsChopped << 2).asFixedPoint(2.BP)
   io.out := lsbsZeroed === io.in
-  printf(s"io_in %x (%d), io_out %d, lsbsChopped %x, lsbsZeroed %x\n",
+  printf("io_in %x (%d), io_out %d, lsbsChopped %x, lsbsZeroed %x\n",
     io.in.asUInt, io.in.asUInt, io.out, lsbsChopped.asUInt, lsbsZeroed.asUInt)
 }