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[sboom] Move TraceIO fragment to chipyard #492

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Mar 19, 2020
Merged

[sboom] Move TraceIO fragment to chipyard #492

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5 changes: 3 additions & 2 deletions generators/chipyard/src/main/scala/ConfigFragments.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
import freechips.rocketchip.util.{AsyncResetReg}

import boom.common.{BoomTilesKey}

import ariane.{ArianeTilesKey}
import testchipip._

import hwacha.{Hwacha}
Expand Down Expand Up @@ -151,7 +151,8 @@ class WithControlCore extends Config((site, here, up) => {
case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
})

class WithBoomTraceIO extends Config((site, here, up) => {
class WithTraceIO extends Config((site, here, up) => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
case TracePortKey => Some(TracePortParams())
})
42 changes: 21 additions & 21 deletions generators/chipyard/src/main/scala/config/BoomConfigs.scala
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Expand Up @@ -6,27 +6,6 @@ import freechips.rocketchip.config.{Config}
// BOOM Configs
// ---------------------

class DromajoBoomConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
new chipyard.iobinders.WithSimDromajoBridge ++
new chipyard.config.WithBoomTraceIO ++
new testchipip.WithTSI ++ // use testchipip serial offchip link
new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks)
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new boom.common.WithMegaBooms ++
new boom.common.WithNBoomCores(1) ++ // single-core boom
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system

class SmallBoomConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
Expand Down Expand Up @@ -184,3 +163,24 @@ class LoopbackNICLargeBoomConfig extends Config(
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.system.BaseConfig)

class DromajoBoomConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new chipyard.iobinders.WithSimDromajoBridge ++ // attach Dromajo
new testchipip.WithTSI ++
new chipyard.config.WithTraceIO ++ // enable the traceio
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithMegaBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.system.BaseConfig)

9 changes: 1 addition & 8 deletions generators/firechip/src/main/scala/TargetConfigs.scala
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Expand Up @@ -74,23 +74,16 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)



// Enables tracing on all cores
class WithTraceIO extends Config((site, here, up) => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
case TracePortKey => Some(TracePortParams())
})


// Tweaks that are generally applied to all firesim configs
class WithFireSimConfigTweaks extends Config(
new WithBootROM ++ // needed to support FireSim-as-top
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ // 3.2 GHz
new WithoutClockGating ++
new WithTraceIO ++
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // 16 GB
new testchipip.WithTSI ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithTraceIO ++
new chipyard.config.WithUART
)

Expand Down