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move traceio back into testchipip #488

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merged 1 commit into from
Mar 19, 2020
Merged

move traceio back into testchipip #488

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2 changes: 1 addition & 1 deletion generators/boom
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Submodule boom updated 1 files
+2 −6 src/main/scala/common/tile.scala
2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/ConfigFragments.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ import hwacha.{Hwacha}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._

import chipyard.{BuildTop, TracePortKey, TracePortParams}
import chipyard.{BuildTop}

/**
* TODO: Why do we need this?
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2 changes: 0 additions & 2 deletions generators/chipyard/src/main/scala/IOBinders.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -16,8 +16,6 @@ import testchipip._
import icenet._
import tracegen.{HasTraceGenTilesModuleImp}

import chipyard.{CanHaveTraceIOModuleImp}

import scala.reflect.{ClassTag}

// System for instantiating binders based
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4 changes: 2 additions & 2 deletions generators/chipyard/src/main/scala/TestHarness.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@ import chisel3.experimental._

import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}

import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.util.GeneratorApp
import freechips.rocketchip.util.{GeneratorApp}
import freechips.rocketchip.devices.debug.{Debug}

import chipyard.config.ConfigValName._
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4 changes: 2 additions & 2 deletions generators/chipyard/src/main/scala/Top.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ import freechips.rocketchip.devices.tilelink._

// DOC include start: Top
class Top(implicit p: Parameters) extends System
with chipyard.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
Expand All @@ -27,7 +27,7 @@ class Top(implicit p: Parameters) extends System
}

class TopModule[+L <: Top](l: L) extends SystemModule(l)
with chipyard.CanHaveTraceIOModuleImp
with testchipip.CanHaveTraceIOModuleImp
with testchipip.CanHavePeripheryBlockDeviceModuleImp
with testchipip.CanHavePeripherySerialModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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77 changes: 0 additions & 77 deletions generators/chipyard/src/main/scala/TraceIO.scala
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2 changes: 1 addition & 1 deletion generators/testchipip
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Submodule testchipip updated 1 files
+85 −3 src/main/scala/TraceIO.scala