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Name all the generated ClockDomains #1891

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merged 1 commit into from
May 30, 2024
Merged

Name all the generated ClockDomains #1891

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3 changes: 2 additions & 1 deletion generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement

// Set up clock domain
private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
.suggestName("chipyard_prcictrl_domain")

val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
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2 changes: 1 addition & 1 deletion generators/rocket-chip
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Submodule rocket-chip updated 5 files
+1 −1 src/main/scala/devices/tilelink/BootROM.scala
+1 −1 src/main/scala/devices/tilelink/CLINT.scala
+1 −1 src/main/scala/devices/tilelink/Plic.scala
+2 −0 src/main/scala/prci/ClockDomain.scala
+3 −2 src/main/scala/tilelink/BusWrapper.scala
2 changes: 1 addition & 1 deletion generators/rocket-chip-blocks
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Submodule rocket-chip-blocks updated 1 files
+1 −1 src/main/scala/devices/uart/UART.scala
2 changes: 1 addition & 1 deletion generators/testchipip
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Submodule testchipip updated 6 files
+4 −0 src/main/resources/testchipip/csrc/cospike_impl.cc
+1 −1 src/main/scala/serdes/PeripheryTLSerial.scala
+14 −8 src/main/scala/serdes/Serdes.scala
+7 −0 src/main/scala/serdes/SerialPhy.scala
+2 −2 src/main/scala/soc/Configs.scala
+1 −0 src/main/scala/soc/Scratchpad.scala
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