[tracegen] Add tracegen support for the BOOM L1D

ucb-bar · Dec 14, 2019 · f6ebd08 · f6ebd08
1 parent 72f9730
commit f6ebd08
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Showing 7 changed files with 287 additions and 8 deletions.
diff --git a/.circleci/config.yml b/.circleci/config.yml
@@ -317,6 +317,35 @@ jobs:
                 key: tracegen-{{ .Branch }}-{{ .Revision }}
                 paths:
                     - "/home/riscvuser/project"
+    prepare-tracegen-boom:
+        docker:
+            - image: riscvboom/riscvboom-images:0.0.12
+        environment:
+            JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
+            TERM: dumb
+        steps:
+            - add_ssh_keys:
+                fingerprints:
+                    - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e"
+            - checkout
+            - run:
+                name: Create hash of toolchains
+                command: |
+                    .circleci/create-hash.sh
+            - restore_cache:
+                keys:
+                    - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
+            - restore_cache:
+                keys:
+                    - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
+            - run:
+                name: Building the tracegen-boom subproject using Verilator
+                command: .circleci/do-rtl-build.sh tracegen-boom
+                no_output_timeout: 120m
+            - save_cache:
+                key: tracegen-boom-{{ .Branch }}-{{ .Revision }}
+                paths:
+                    - "/home/riscvuser/project"
     prepare-firesim:
         docker:
             - image: riscvboom/riscvboom-images:0.0.12
@@ -540,6 +569,30 @@ jobs:
             - run:
                 name: Run tracegen tests
                 command: .circleci/run-tests.sh tracegen
+    tracegen-boom-run-tests:
+        docker:
+            - image: riscvboom/riscvboom-images:0.0.12
+        environment:
+            JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
+            TERM: dumb
+        steps:
+            - checkout
+            - run:
+                name: Create hash of toolchains
+                command: |
+                    .circleci/create-hash.sh
+            - restore_cache:
+                keys:
+                    - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
+            - restore_cache:
+                keys:
+                    - tracegen-boom-{{ .Branch }}-{{ .Revision }}
+            - restore_cache:
+                keys:
+                    - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
+            - run:
+                name: Run tracegen-boom tests
+                command: .circleci/run-tests.sh tracegen-boom
     firesim-run-tests:
         docker:
             - image: riscvboom/riscvboom-images:0.0.12
@@ -665,6 +718,11 @@ workflows:
                     - install-riscv-toolchain
                     - install-verilator
 
+            - prepare-tracegen-boom:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
             - prepare-firesim:
                 requires:
                     - install-riscv-toolchain
@@ -708,6 +766,10 @@ workflows:
                 requires:
                     - prepare-tracegen
 
+            - tracegen-boom-run-tests:
+                requires:
+                    - prepare-tracegen-boom
+
             # Run the firesim tests
             - firesim-run-tests:
                 requires:

diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh
@@ -48,5 +48,6 @@ mapping["rocketchip"]="SUB_PROJECT=rocketchip"
 mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
 mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig"
 mapping["tracegen"]="SUB_PROJECT=tracegen CONFIG=NonBlockingTraceGenL2Config"
+mapping["tracegen-boom"]="SUB_PROJECT=tracegen CONFIG=BoomTraceGenConfig"
 mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"
 mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config"
diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh
@@ -53,6 +53,9 @@ case $1 in
     tracegen)
         run_tracegen ${mapping[$1]}
         ;;
+    tracegen-boom)
+        run_tracegen ${mapping[$1]}
+        ;;
     *)
         echo "No set of tests for $1. Did you spell it right?"
         exit 1

diff --git a/build.sbt b/build.sbt
@@ -127,7 +127,7 @@ lazy val example = conditionalDependsOn(project in file("generators/example"))
   .settings(commonSettings)
 
 lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
-  .dependsOn(rocketchip, sifive_cache)
+  .dependsOn(rocketchip, sifive_cache, boom)
   .settings(commonSettings)
 
 lazy val utilities = conditionalDependsOn(project in file("generators/utilities"))

diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala
@@ -10,7 +10,7 @@ import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
 import scala.math.{max, min}
 
-class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
+class WithTraceGen(params: Seq[DCacheParams], boom_params: Seq[DCacheParams] = Nil, nReqs: Int = 8192)
     extends Config((site, here, up) => {
   case TraceGenKey => params.map { dcp => TraceGenParams(
     dcache = Some(dcp),
@@ -32,7 +32,28 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
     memStart = site(ExtMem).get.master.base,
     numGens = params.size)
   }
-  case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
+  case BoomTraceGenKey => boom_params.map { dcp => TraceGenParams(
+    dcache = Some(dcp),
+    wordBits = site(XLen),
+    addrBits = 48,
+    addrBag = {
+      val nSets = dcp.nSets
+      val nWays = dcp.nWays
+      val blockOffset = site(SystemBusKey).blockOffset
+      val nBeats = min(2, site(SystemBusKey).blockBeats)
+      val beatBytes = site(SystemBusKey).beatBytes
+      List.tabulate(2 * nWays) { i =>
+        Seq.tabulate(nBeats) { j =>
+          BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
+        }
+      }.flatten
+    },
+    maxRequests = nReqs,
+    memStart = site(ExtMem).get.master.base,
+    numGens = params.size)
+  }
+  case MaxHartIdBits => if (params.size + boom_params.size == 1) 1
+      else log2Ceil(params.size + boom_params.size)
 })
 
 class TraceGenConfig extends Config(
@@ -43,6 +64,10 @@ class NonBlockingTraceGenConfig extends Config(
   new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
   new BaseConfig)
 
+class BoomTraceGenConfig extends Config(
+  new WithTraceGen(Nil, List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
+  new BaseConfig)
+
 class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
     extends Config((site, here, up) => {
   case TraceGenKey => params.map { dcp => TraceGenParams(

diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
@@ -6,12 +6,18 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
 import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams}
 import freechips.rocketchip.subsystem._
 
-case object TraceGenKey extends Field[Seq[TraceGenParams]]
+case object BoomTraceGenKey extends Field[Seq[TraceGenParams]](Nil)
+case object TraceGenKey extends Field[Seq[TraceGenParams]](Nil)
 
 trait HasTraceGenTiles { this: BaseSubsystem =>
-  val tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) =>
+  val rocket_tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) =>
     LazyModule(new TraceGenTile(i, params, p))
   }
+  val boom_tiles = p(BoomTraceGenKey).zipWithIndex.map { case (params, i) =>
+    LazyModule(new BoomTraceGenTile(i, params, p))
+  }
+
+  val tiles = rocket_tiles ++ boom_tiles
 
   tiles.foreach { t =>
     sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode }
@@ -26,7 +32,10 @@ trait HasTraceGenTilesModuleImp extends LazyModuleImp {
     t.module.constants.hartid := i.U
   }
 
-  val status = DebugCombiner(outer.tiles.map(_.module.status))
+  val status = DebugCombiner(
+    outer.rocket_tiles.map(_.module.status) ++
+    outer.boom_tiles.map(_.module.status)
+  )
   success := status.finished
 }