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Update to chisel 3.2.x #75
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jwright6323
approved these changes
Feb 24, 2020
| mem_0_3.clk <= clk | ||
| mem_0_3.addr <= addr | ||
| node dout_0_3 = bits(mem_0_3.dout, 31, 0) | ||
| mem_0_3.din <= bits(din, 127, 96) | ||
| mem_0_3.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) | ||
| mem_0_3.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) |
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I assume this is due to a FIRRTL change, but where did this extra redundant and with 1 come from?
| } |
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This file seems fine but is harder to review with all the whitespace removal :(
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For ucb-bar/chipyard#438