Implementation of the Wave-U-Net for audio source separation
-
Updated
Mar 24, 2023 - Python
#
waveform-analysis
Here are 13 public repositories matching this topic...
Problem Agnostic Speech Encoder
deep-learning pytorch unsupervised-learning speech-processing multi-task-learning waveform-analysis self-supervised-learning
-
Updated
Jul 6, 2023 - Python
Audio input -> real-time analysis -> OSC output. Takes in real-time audio, does feature extraction using smart algorithms then sends out OSC to be used in other programs.
nodejs machine-learning real-time audio-features audio-analysis music-information-retrieval music-visualizer fft open-sound-control digital-signal-processing beat-tracking bpm-detection waveform-analysis live-audio audio-feature-extraction
-
Updated
Mar 31, 2022
Scripts for M-LARGE training and analysis
-
Updated
Mar 28, 2023 - Python
A GUI to draw your own waveform in the time or frequency domain and play with a MIDI keyboard.
react gui midi reactjs waveform sound-processing music-theory music-visualizer educational user-interface digital-signal-processing waveform-visualizer waveform-analysis waveform-generator music-education old-school-game
-
Updated
Aug 7, 2024 - JavaScript
Eridian to English Translator as described in Andy Weirs 'Project Hail Mary'
-
Updated
Jul 2, 2024 - Python
Gate-level implementation of a half-subtractor using Verilog, featuring a comprehensive testbench, truth table validation, and waveform analysis for beginners in digital design.
verilog icarus-verilog gtkwave waveform-analysis digital-logic-design logic-circuits vlsi-design half-subtractor
-
Updated
Jan 18, 2025 - Verilog
Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
open-source verilog mux icarus-verilog gtkwave multiplexer testbench waveform-analysis digital-logic-design vlsi-design gate-level-simulation
-
Updated
Jan 12, 2025 - Verilog
Simulate and analyze fundamental logic gates using Icarus Verilog and GTKWave. This project provides a modular Verilog implementation and a comprehensive testbench for precise validation, offering valuable insights into digital design workflows for VLSI professionals.
open-source asic simulation verilog logic-gates gtkwave hdl vlsi testbench iverilog digital-design waveform-analysis rtl-design
-
Updated
Jan 26, 2025 - Verilog
A compact Verilog project implementing a half-adder with gate-level modeling, featuring a detailed testbench for functional verification and simulation.
-
Updated
Feb 2, 2025 - Verilog
Kevin Macon's trapezoidal filtering code for waveform analysis out of digitizers. And helpful tidbits added by me.
-
Updated
Oct 3, 2017 - C
Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
verilog icarus-verilog gtkwave testbench waveform-analysis digital-logic-design full-adder logic-circuits vlsi-design gate-level-simulation
-
Updated
Jan 6, 2025 - Verilog
Improve this page
Add a description, image, and links to the waveform-analysis topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the waveform-analysis topic, visit your repo's landing page and select "manage topics."