This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
Universal Asynchronous Receiver-Transmitter (UART) loopback on the VSD Squadcom Mini FPGA board
VSDSquadron FPGA Mini Board Research Internship by Ojasvi Shah
The Samsung RISC-V Workshop offers hands-on training in SoC design using the VSD Squadron Mini board, covering RISC-V ISA, toolchains, and system design, with an industry-recognized certification.
Add a description, image, and links to the vsd topic page so that developers can more easily learn about it.
To associate your repository with the vsd topic, visit your repo's landing page and select "manage topics."