OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

The next generation of OpenLane, rewritten from scratch with a modular architecture

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

AMC: Asynchronous Memory Compiler

design and verification of asynchronous circuits

Gate-level visualization generator for SKY130-based chip designs.

genetic algorithm usage for routing optimization ( pyqt )

Automated custom cell layout generator

Simulated Annealing to minimize the wirelength

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

Python-based IP-XACT parser

RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Combinatorial Decision Making and Optimization project on Very Large Scale Integration (VLSI) with Constraint Programming (CP), propositional SATisfiability (SAT), and Satisfiability Modulo Theories (SMT)

Micro-Framework for FPGA / VLSI Design Flow in Python

Python implementation of the Leiserson retiming graph algorithms

Given a simple VLSI (Very Large Scale Integration), use Constraint Programming, SAT and SMT solver, to provide the solution with the minimum height of the silicon chip

Digital cell library designed in Magic for the TSMC 180nm process, with an accompanying data book generator script

EC804 Digital VLSI Testing and Testability Assignments.

The VLSI problem requires to fit all the rectangles in the grid without overlapping one on an another, by minimizing the height of the grid.