The Refreshingly Simple Cross-Platform C++ Dataflow / Patching / Pipelining / Graph Processing / Stream Processing / Reactive Programming Framework

Cross-Platform Graphical Tool for DSPatch

DSPatch Component Repository

Kite: Architecture Simulator for RISC-V Instruction Set

CSE-306-Computer-Architecture Offline / Assignment on ALU, Floating Point Adder and 8 bit MIPS Datapath along with pipelining

Cross-Platform C++ Dataflow / Pipelining / Stream Processing / Reactive Metaprogramming Framework

A C++ pipeline based simulator of RSIC architecture.

A 5-stage CPU pipeline simulator based on the well-known Tomasulo algorithm.

Assignments done in Computer Architecture course.

Simulation of 5-stage pipelined processor based on MIPS assembly language. Course Project as part of our CSN-221, Computer Architecture course at IIT Roorkee.