Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP

DMA source and sink blocks for Xilinx Zynq FPGAs

Example of transfer UDP packets from AXI DMA with SG mode.

Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.

Some of small codes and implementation of modules in Computer Aided Design in VHDL by ActiveHDL

ADS1115 Communication with AXI interface example with zybo board

Repository for DSP matrix multiplier IP core and other related side projects

forked Digilent Demo