Digital Logical Designs Course Projects
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Updated
Aug 19, 2022 - Verilog
Digital Logical Designs Course Projects
This is 32 Bit Parallel Prefix Adder using Verilog.
Add a description, image, and links to the dld-project topic page so that developers can more easily learn about it.
To associate your repository with the dld-project topic, visit your repo's landing page and select "manage topics."