A data lab at UiO (FYS4220, Lab 1, 2019) in VHDL design using Quartus
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Jan 9, 2020 - VHDL
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de1-soc-board
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The work presented is designed to simulate the operation of an automatic coffee machine. It will manage the machine operation by exploiting the processing capabilities of the FPGA.
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Dec 16, 2019 - VHDL
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