Modifications to support simple CGRA RTL->Layout. #20
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tancheng
reviewed
Oct 17, 2024
cgra/translate/CGRARTL_test.py
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| num_fu_in = 4 | ||
| DUT = CGRARTL | ||
| FunctionUnit = FlexibleFuRTL | ||
| FuList = [ SeqMulAdderRTL, MemUnitRTL ]#AdderRTL, MulRTL, LogicRTL, ShifterRTL, PhiRTL, CompRTL, BranchRTL, MemUnitRTL ] | ||
| DataType = mk_data( 32, 1 ) | ||
| FuList = [ AdderRTL, MemUnitRTL ]#AdderRTL, MulRTL, LogicRTL, ShifterRTL, PhiRTL, CompRTL, BranchRTL, MemUnitRTL ] |
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Plz replace the #AdderRTL with # SeqMulAdderRTL, AdderRTL.
cgra/translate/CGRARTL_test.py
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| FuList = [ SeqMulAdderRTL, MemUnitRTL ]#AdderRTL, MulRTL, LogicRTL, ShifterRTL, PhiRTL, CompRTL, BranchRTL, MemUnitRTL ] | ||
| DataType = mk_data( 32, 1 ) | ||
| FuList = [ AdderRTL, MemUnitRTL ]#AdderRTL, MulRTL, LogicRTL, ShifterRTL, PhiRTL, CompRTL, BranchRTL, MemUnitRTL ] | ||
| DataType = mk_data( 16, 1 ) |
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Replace this line as follows:
# Parameterizes channel bandwidth as around 2-byte per cycle.
payload_nbits = 16 # 32
predicate_nbits = 1
DataType = mk_data( payload_nbits, predicate_nbits )
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Hi @yyan7223, let's update this and submit? |
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Sorry I forget last week, and I have updated the code as you required. |
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Modifications to support the CGRA-Flow generated RTL to Layout.