Merge branch 'master' into separate_xbar

tancheng · Nov 30, 2024 · 854b826 · 854b826
2 parents 9e2ae90 + 8441c66
commit 854b826
Show file tree

Hide file tree

Showing 13 changed files with 1,051 additions and 30 deletions.
diff --git a/.github/workflows/python-package.yml b/.github/workflows/python-package.yml
@@ -62,4 +62,7 @@ jobs:
         pytest ../cgra/translate/VectorCGRAKingMeshRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
         pytest ../tile/translate/TileRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
         pytest ../cgra/translate/CGRASeparateCrossbarRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
+        pytest ../cgra/translate/CGRAMemBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
+        pytest ../cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short
+        pytest ../cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
 
diff --git a/cgra/CGRAMemBottomRTL.py b/cgra/CGRAMemBottomRTL.py
@@ -0,0 +1,116 @@
+"""
+=========================================================================
+CGRAMemBottomRTL.py
+=========================================================================
+The scrachpad memory is connected to the bottom (first row) tiles.
+
+Author : Cheng Tan
+  Date : Nov 18, 2024
+"""
+
+from pymtl3                      import *
+from ..lib.ifcs                  import SendIfcRTL, RecvIfcRTL
+from ..noc.CrossbarRTL           import CrossbarRTL
+from ..noc.ChannelRTL            import ChannelRTL
+from ..tile.TileRTL              import TileRTL
+from ..lib.opt_type              import *
+from ..lib.common                import *
+from ..mem.data.DataMemRTL       import DataMemRTL
+from ..mem.data.DataMemCL        import DataMemCL
+from ..fu.single.MemUnitRTL      import MemUnitRTL
+from ..fu.single.AdderRTL        import AdderRTL
+from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL
+
+class CGRAMemBottomRTL(Component):
+
+  def construct(s, DataType, PredicateType, CtrlType, width, height,
+                ctrl_mem_size, data_mem_size, num_ctrl, total_steps,
+                FunctionUnit, FuList, preload_data = None,
+                preload_const = None):
+
+    s.num_tiles = width * height
+    s.num_mesh_ports = 4
+    AddrType = mk_bits(clog2(ctrl_mem_size))
+
+    # Interfaces
+    s.recv_waddr = [RecvIfcRTL(AddrType) for _ in range(s.num_tiles)]
+    s.recv_wopt = [RecvIfcRTL(CtrlType) for _ in range(s.num_tiles)]
+
+    # Components
+    if preload_const == None:
+      preload_const = [[DataType(0, 0)] for _ in range(width * height)]
+    s.tile = [TileRTL(DataType, PredicateType, CtrlType,
+                      ctrl_mem_size, data_mem_size, num_ctrl,
+                      total_steps, 4, 2, s.num_mesh_ports,
+                      s.num_mesh_ports, Fu = FunctionUnit,
+                      FuList = FuList, const_list = preload_const[i])
+                      for i in range(s.num_tiles)]
+    s.data_mem = DataMemRTL(DataType, data_mem_size, height, height,
+                            preload_data)
+
+    s.send_data = [SendIfcRTL(DataType) for _ in range (height - 1)]
+
+    # Connections
+    for i in range(s.num_tiles):
+      s.recv_waddr[i] //= s.tile[i].recv_waddr
+      s.recv_wopt[i] //= s.tile[i].recv_wopt
+
+      if i // width > 0:
+        s.tile[i].send_data[PORT_SOUTH] //= s.tile[i-width].recv_data[PORT_NORTH]
+
+      if i // width < height - 1:
+        s.tile[i].send_data[PORT_NORTH] //= s.tile[i+width].recv_data[PORT_SOUTH]
+
+      if i % width > 0:
+        s.tile[i].send_data[PORT_WEST] //= s.tile[i-1].recv_data[PORT_EAST]
+
+      if i % width < width - 1:
+        s.tile[i].send_data[PORT_EAST] //= s.tile[i+1].recv_data[PORT_WEST]
+
+      if i // width == 0:
+        s.tile[i].send_data[PORT_SOUTH].rdy //= 0
+        s.tile[i].recv_data[PORT_SOUTH].en //= 0
+        s.tile[i].recv_data[PORT_SOUTH].msg //= DataType(0, 0)
+
+      if i // width == height - 1:
+        s.tile[i].send_data[PORT_NORTH].rdy //= 0
+        s.tile[i].recv_data[PORT_NORTH].en //= 0
+        s.tile[i].recv_data[PORT_NORTH].msg //= DataType(0, 0)
+
+      if i % width == 0:
+        s.tile[i].send_data[PORT_WEST].rdy //= 0
+        s.tile[i].recv_data[PORT_WEST].en //= 0
+        s.tile[i].recv_data[PORT_WEST].msg //= DataType(0, 0)
+
+      if i % width == width - 1:
+        if i // width != 0:
+          # Connects the send ports to the right-most tiles (except the
+          # ones on the first row).
+          s.tile[i].send_data[PORT_EAST] //= s.send_data[i // width - 1]
+          s.tile[i].recv_data[PORT_EAST].en //= 0
+          s.tile[i].recv_data[PORT_EAST].msg //= DataType(0, 0)
+        else:
+          s.tile[i].send_data[PORT_EAST].rdy //= 0
+          s.tile[i].recv_data[PORT_EAST].en //= 0
+          s.tile[i].recv_data[PORT_EAST].msg //= DataType(0, 0)
+
+      if i // width == 0:
+        s.tile[i].to_mem_raddr //= s.data_mem.recv_raddr[i % width]
+        s.tile[i].from_mem_rdata //= s.data_mem.send_rdata[i % width]
+        s.tile[i].to_mem_waddr //= s.data_mem.recv_waddr[i % width]
+        s.tile[i].to_mem_wdata //= s.data_mem.recv_wdata[i % width]
+      else:
+        s.tile[i].to_mem_raddr.rdy //= 0
+        s.tile[i].from_mem_rdata.en //= 0
+        s.tile[i].from_mem_rdata.msg //= DataType(0, 0)
+        s.tile[i].to_mem_waddr.rdy //= 0
+        s.tile[i].to_mem_wdata.rdy //= 0
+
+  # Line trace
+  def line_trace(s):
+    # str = "||".join([ x.element.line_trace() for x in s.tile ])
+    # str += " :: [" + s.data_mem.line_trace() + "]"
+    res = "||\n".join([(("[tile" + str(i) + "]: ") + x.line_trace() + x.ctrl_mem.line_trace())
+                       for (i,x) in enumerate(s.tile)])
+    res += "\n :: Mem [" + s.data_mem.line_trace() + "]    \n"
+    return res
diff --git a/cgra/CGRAMemRightAndBottomRTL.py b/cgra/CGRAMemRightAndBottomRTL.py
@@ -0,0 +1,135 @@
+"""
+=========================================================================
+CGRAMemRightAndBottomRTL.py
+=========================================================================
+Two scrachpad memories are connected to the bottom (first row) and the
+last column (except the one on the first row) tiles. For example, in a
+3x3 CGRA, the bottom 3 tiles are connected to the south SPM while right-
+most 2 tlies (from top to bottom) are connected to the east SPM.
+
+Author : Cheng Tan
+  Date : Nov 19, 2024
+"""
+
+from pymtl3                      import *
+from ..lib.ifcs                  import SendIfcRTL, RecvIfcRTL
+from ..noc.CrossbarRTL           import CrossbarRTL
+from ..noc.ChannelRTL            import ChannelRTL
+from ..tile.TileRTL              import TileRTL
+from ..lib.opt_type              import *
+from ..lib.common                import *
+from ..mem.data.DataMemRTL       import DataMemRTL
+from ..mem.data.DataMemCL        import DataMemCL
+from ..fu.single.MemUnitRTL      import MemUnitRTL
+from ..fu.single.AdderRTL        import AdderRTL
+from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL
+
+class CGRAMemRightAndBottomRTL(Component):
+
+  def construct(s, DataType, PredicateType, CtrlType, width, height,
+                ctrl_mem_size, data_mem_size, num_ctrl, total_steps,
+                FunctionUnit, FuList, preload_data = None,
+                preload_const = None):
+
+    s.num_tiles = width * height
+    s.num_mesh_ports = 4
+    AddrType = mk_bits(clog2(ctrl_mem_size))
+
+    # Interfaces
+    s.recv_waddr = [RecvIfcRTL(AddrType) for _ in range(s.num_tiles)]
+    s.recv_wopt = [RecvIfcRTL(CtrlType) for _ in range(s.num_tiles)]
+
+    # Components
+    if preload_const == None:
+      preload_const = [[DataType(0, 0)] for _ in range(width * height)]
+    s.tile = [TileRTL(DataType, PredicateType, CtrlType,
+                      ctrl_mem_size, data_mem_size, num_ctrl,
+                      total_steps, 4, 2, s.num_mesh_ports,
+                      s.num_mesh_ports, Fu = FunctionUnit,
+                      FuList = FuList, const_list = preload_const[i])
+                      for i in range(s.num_tiles)]
+
+    s.data_mem_south = DataMemRTL(DataType, data_mem_size,
+                                  rd_ports = width, wr_ports = width,
+                                  preload_data = preload_data)
+
+    s.data_mem_east = DataMemRTL(DataType, data_mem_size,
+                                 rd_ports = height - 1,
+                                 wr_ports = height - 1,
+                                 preload_data = None)
+
+    # s.send_data = [SendIfcRTL(DataType) for _ in range (height - 1)]
+
+    # Connections
+    for i in range(s.num_tiles):
+      s.recv_waddr[i] //= s.tile[i].recv_waddr
+      s.recv_wopt[i] //= s.tile[i].recv_wopt
+
+      if i // width > 0:
+        s.tile[i].send_data[PORT_SOUTH] //= s.tile[i-width].recv_data[PORT_NORTH]
+
+      if i // width < height - 1:
+        s.tile[i].send_data[PORT_NORTH] //= s.tile[i+width].recv_data[PORT_SOUTH]
+
+      if i % width > 0:
+        s.tile[i].send_data[PORT_WEST] //= s.tile[i-1].recv_data[PORT_EAST]
+
+      if i % width < width - 1:
+        s.tile[i].send_data[PORT_EAST] //= s.tile[i+1].recv_data[PORT_WEST]
+
+      if i // width == 0:
+        s.tile[i].send_data[PORT_SOUTH].rdy //= 0
+        s.tile[i].recv_data[PORT_SOUTH].en //= 0
+        s.tile[i].recv_data[PORT_SOUTH].msg //= DataType(0, 0)
+
+      if i // width == height - 1:
+        s.tile[i].send_data[PORT_NORTH].rdy //= 0
+        s.tile[i].recv_data[PORT_NORTH].en //= 0
+        s.tile[i].recv_data[PORT_NORTH].msg //= DataType(0, 0)
+
+      if i % width == 0:
+        s.tile[i].send_data[PORT_WEST].rdy //= 0
+        s.tile[i].recv_data[PORT_WEST].en //= 0
+        s.tile[i].recv_data[PORT_WEST].msg //= DataType(0, 0)
+
+      if i % width == width - 1:
+        # if i // width != 0:
+        #   # Connects the send ports to the right-most tiles (except the
+        #   # ones on the first row).
+        #   s.tile[i].send_data[PORT_EAST] //= s.send_data[i // width - 1]
+        #   s.tile[i].recv_data[PORT_EAST].en //= 0
+        #   s.tile[i].recv_data[PORT_EAST].msg //= DataType(0, 0)
+        # else:
+        s.tile[i].send_data[PORT_EAST].rdy //= 0
+        s.tile[i].recv_data[PORT_EAST].en //= 0
+        s.tile[i].recv_data[PORT_EAST].msg //= DataType(0, 0)
+
+      if i // width == 0:
+        # Connects the bottom tiles to the south SPM. 
+        s.tile[i].to_mem_raddr //= s.data_mem_south.recv_raddr[i % width]
+        s.tile[i].from_mem_rdata //= s.data_mem_south.send_rdata[i % width]
+        s.tile[i].to_mem_waddr //= s.data_mem_south.recv_waddr[i % width]
+        s.tile[i].to_mem_wdata //= s.data_mem_south.recv_wdata[i % width]
+      elif i // width != 0 and i % width == width - 1:
+        # Connects the right-most tiles (except the bottom ones) to the east
+        # SPM.
+        s.tile[i].to_mem_raddr //= s.data_mem_east.recv_raddr[i // width - 1]
+        s.tile[i].from_mem_rdata //= s.data_mem_east.send_rdata[i // width - 1]
+        s.tile[i].to_mem_waddr //= s.data_mem_east.recv_waddr[i // width - 1]
+        s.tile[i].to_mem_wdata //= s.data_mem_east.recv_wdata[i // width - 1]
+      else:
+        s.tile[i].to_mem_raddr.rdy //= 0
+        s.tile[i].from_mem_rdata.en //= 0
+        s.tile[i].from_mem_rdata.msg //= DataType(0, 0)
+        s.tile[i].to_mem_waddr.rdy //= 0
+        s.tile[i].to_mem_wdata.rdy //= 0
+
+  # Line trace
+  def line_trace(s):
+    # str = "||".join([ x.element.line_trace() for x in s.tile ])
+    # str += " :: [" + s.data_mem.line_trace() + "]"
+    res = "||\n".join([(("[tile" + str(i) + "]: ") + x.line_trace() + x.ctrl_mem.line_trace())
+                       for (i,x) in enumerate(s.tile)])
+    res += "\n :: SouthMem [" + s.data_mem_south.line_trace() + "]    \n"
+    res += "\n :: EastMem [" + s.data_mem_east.line_trace() + "]    \n"
+    return res
diff --git a/cgra/CGRARTL.py b/cgra/CGRARTL.py
@@ -40,7 +40,10 @@ def construct( s, DataType, PredicateType, CtrlType, width, height,
     s.tile = [ TileRTL( DataType, PredicateType, CtrlType,
                         ctrl_mem_size, data_mem_size, num_ctrl,
                         total_steps, 4, 2, s.num_mesh_ports,
-                        s.num_mesh_ports, const_list = preload_const[i] )
+                        s.num_mesh_ports,
+                        Fu = FunctionUnit,
+                        FuList = FuList,
+                        const_list = preload_const[i] )
                         for i in range( s.num_tiles ) ]
     s.data_mem = DataMemRTL( DataType, data_mem_size, height, height, preload_data )