Merge pull request #63 from rp15/master

Fused functional unit documentation and test clean-up
tancheng · Jan 10, 2025 · 7007b8a · 7007b8a
2 parents 4688d88 + 4bb71db
commit 7007b8a
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diff --git a/fu/fused_alu_fixedp/AluGenMacRTL.py b/fu/fused_alu_fixedp/AluGenMacRTL.py
@@ -111,27 +111,6 @@ def comb_logic():
           s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy
           s.recv_in[s.in2_idx].rdy @= s.recv_all_val & s.send_out[0].rdy
           s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy
-          # FIXME: @RJ, what is the following for?
-          #elif s.recv_opt.msg.ctrl == OPT_FADD_CONST:
-          #  s.fadd.rhs_0 @= s.recv_in[s.in0_idx].msg.payload
-          #  s.fadd.rhs_1 @= s.recv_const.msg.payload
-          #  s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate
-
-          #elif s.recv_opt.msg.ctrl == OPT_FINC:
-          #  s.fadd.rhs_0 @= s.recv_in[s.in0_idx].msg.payload
-          #  s.fadd.rhs_1 @= s.FLOATING_ONE
-          #  s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate
-
-          #elif s.recv_opt.msg.ctrl == OPT_FSUB:
-          #  s.fadd.rhs_0 @= s.recv_in[s.in0_idx].msg.payload
-          #  s.fadd.rhs_1 @= s.recv_in[s.in1_idx].msg.payload
-          #  s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate
-          #  if s.recv_opt.en & ( (s.recv_in_count[s.in0_idx] == 0) | \
-          #                       (s.recv_in_count[s.in1_idx] == 0) ):
-          #    s.recv_in[s.in0_idx].rdy @= b1( 0 )
-          #    s.recv_in[s.in1_idx].rdy @= b1( 0 )
-          #    s.send_out[0].msg.predicate @= b1( 0 )
-
         else:
           for j in range(num_outports):
             s.send_out[j].val @= b1(0)

diff --git a/fu/fused_alu_fixedp/README.md b/fu/fused_alu_fixedp/README.md
@@ -1,3 +1,7 @@
+The fixed-point functional unit's SystemVerilog RTL code is located in svsrc/. At the same level as this README file, there are two PyMTL wrappers. AluGenMacRTL.py encapsulates the SystemVerilog RTL code and makes it compatible with the PyMTL framework. AluGenMacWrapperRTL.py encapsulates the AluGenMacRTL.py SystemVerilog-to-PyMTL wrapper to make it compatible with the VectorCGRA framework. Both levels of abstraction can be verified using their respective tests in the test/ directory.
+
+The SystemVerilog code instantiates a DesignWare module that is linked as an external dependency to this repo. The git submodule update --init command ensures that the submodule is exported correctly, as described in the repo's main README.
+
 Publication
 --------------------------------------------------------
 ```