[Mellanox] Adjust buffer parameters with 2km cable supported for 4600C MSFT SKUs #87
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Also recalculated all parameters with the latest algorithm with per-speed peer response time taken into account Detailed information of each SKU: - C64: 32 100G down links and 32 100G up links with 2km cable supported on t1 - D112C8: 112 50G down links and 8 100G up links. - D48C40: 48 50G down links, 32 100G down links and 8 100G up links - D100C12S2: 4 100G down links, 2 10G down links, 100 50G down links and 8 100G uplinks 2km cable is supported for C64 on t1 only Signed-off-by: Stephen Sun <stephens@nvidia.com>
keboliu
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Nov 10, 2021
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ci passed. session 1049 |
stephenxs
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Mar 21, 2022
e56e9b4 Fix CVE-2021-3121 warning (#96) bf1be4f [ci]: Support code diff coverage threshold 50% (#94) 64e516c Ported Marvell armhf build on x86 for debian buster to use cross-compilation instead of qemu emulation (#80) e426388 [ci]: Support azp code coverage (#87)
stephenxs
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that referenced
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Mar 25, 2022
e56e9b4 Fix CVE-2021-3121 warning (#96) bf1be4f [ci]: Support code diff coverage threshold 50% (#94) 64e516c Ported Marvell armhf build on x86 for debian buster to use cross-compilation instead of qemu emulation (#80) e426388 [ci]: Support azp code coverage (#87)
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Why I did it
Also recalculated all parameters with the latest algorithm with per-speed peer response time taken into account
Signed-off-by: Stephen Sun stephens@nvidia.com
How I did it
Detailed information of each SKU:
2km cable is supported for C64 on t1 only
How to verify it
Run regression test (QoS)
Which release branch to backport (provide reason below if selected)
Description for the changelog
A picture of a cute animal (not mandatory but encouraged)