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[202305][ppi]: Implement port bulk comparison logic #2921

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merged 1 commit into from
Oct 11, 2023
Merged

[202305][ppi]: Implement port bulk comparison logic #2921

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2 changes: 2 additions & 0 deletions orchagent/Makefile.am
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@ INCLUDES = -I $(top_srcdir)/lib \
-I $(top_srcdir)/warmrestart \
-I flex_counter \
-I debug_counter \
-I port \
-I pbh \
-I nhg

Expand Down Expand Up @@ -56,6 +57,7 @@ orchagent_SOURCES = \
mplsrouteorch.cpp \
neighorch.cpp \
intfsorch.cpp \
port/porthlpr.cpp \
portsorch.cpp \
fabricportsorch.cpp \
fgnhgorch.cpp \
Expand Down
6 changes: 3 additions & 3 deletions orchagent/mirrororch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -588,7 +588,7 @@ void MirrorOrch::setSessionState(const string& name, const MirrorEntry& session,
Port port;
if ((gMySwitchType == "voq") && (session.type == MIRROR_SESSION_ERSPAN))
{
if (!m_portsOrch->getRecircPort(port, "Rec"))
if (!m_portsOrch->getRecircPort(port, Port::Role::Rec))
{
SWSS_LOG_ERROR("Failed to get recirc port for mirror session %s", name.c_str());
return;
Expand Down Expand Up @@ -946,7 +946,7 @@ bool MirrorOrch::activateSession(const string& name, MirrorEntry& session)
if (gMySwitchType == "voq")
{
Port recirc_port;
if (!m_portsOrch->getRecircPort(recirc_port, "Rec"))
if (!m_portsOrch->getRecircPort(recirc_port, Port::Role::Rec))
{
SWSS_LOG_ERROR("Failed to get recirc port");
return false;
Expand Down Expand Up @@ -1177,7 +1177,7 @@ bool MirrorOrch::updateSessionDstPort(const string& name, MirrorEntry& session)
// Set monitor port to recirc port in voq switch.
if ((gMySwitchType == "voq") && (session.type == MIRROR_SESSION_ERSPAN))
{
if (!m_portsOrch->getRecircPort(port, "Rec"))
if (!m_portsOrch->getRecircPort(port, Port::Role::Rec))
{
SWSS_LOG_ERROR("Failed to get recirc port for mirror session %s", name.c_str());
return false;
Expand Down
4 changes: 2 additions & 2 deletions orchagent/orch.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@
#include <utility>

extern "C" {
#include "sai.h"
#include "saistatus.h"
#include <sai.h>
#include <saistatus.h>
}

#include "dbconnector.h"
Expand Down
45 changes: 10 additions & 35 deletions orchagent/p4orch/tests/fake_portorch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -322,7 +322,7 @@ bool PortsOrch::setVoqInbandIntf(string &alias, string &type)
return true;
}

bool PortsOrch::getRecircPort(Port &p, string role)
bool PortsOrch::getRecircPort(Port &p, Port::Role role)
{
return true;
}
Expand Down Expand Up @@ -443,7 +443,7 @@ bool PortsOrch::setHostIntfsStripTag(Port &port, sai_hostif_vlan_tag_t strip)
return true;
}

bool PortsOrch::setBridgePortLearnMode(Port &port, string learn_mode)
bool PortsOrch::setBridgePortLearnMode(Port &port, sai_bridge_port_fdb_learning_mode_t learn_mode)
{
return true;
}
Expand Down Expand Up @@ -493,17 +493,12 @@ bool PortsOrch::setDistributionOnLagMember(Port &lagMember, bool enableDistribut
return true;
}

bool PortsOrch::addPort(const set<int> &lane_set, uint32_t speed, int an, string fec)
{
return true;
}

sai_status_t PortsOrch::removePort(sai_object_id_t port_id)
{
return SAI_STATUS_SUCCESS;
}

bool PortsOrch::initPort(const string &alias, const string &role, const int index, const set<int> &lane_set)
bool PortsOrch::initPort(const PortConfig &port)
{
return true;
}
Expand All @@ -527,7 +522,7 @@ bool PortsOrch::setPortMtu(const Port &port, sai_uint32_t mtu)
return true;
}

bool PortsOrch::setPortTpid(sai_object_id_t id, sai_uint16_t tpid)
bool PortsOrch::setPortTpid(Port &port, sai_uint16_t tpid)
{
return true;
}
Expand All @@ -542,12 +537,12 @@ bool PortsOrch::getPortPvid(Port &port, sai_uint32_t &pvid)
return true;
}

bool PortsOrch::setPortFec(Port &port, std::string &mode)
bool PortsOrch::setPortFec(Port &port, sai_port_fec_mode_t fec_mode)
{
return true;
}

bool PortsOrch::setPortPfcAsym(Port &port, string pfc_asym)
bool PortsOrch::setPortPfcAsym(Port &port, sai_port_priority_flow_control_mode_t pfc_asym)
{
return true;
}
Expand Down Expand Up @@ -596,7 +591,7 @@ bool PortsOrch::setGearboxPortAttr(const Port &port, dest_port_type_t port_type,
return true;
}

task_process_status PortsOrch::setPortAdvSpeeds(sai_object_id_t port_id, std::vector<sai_uint32_t> &speed_list)
task_process_status PortsOrch::setPortAdvSpeeds(Port &port, std::set<sai_uint32_t> &speed_list)
{
return task_success;
}
Expand All @@ -611,22 +606,17 @@ bool PortsOrch::isAutoNegEnabled(sai_object_id_t id)
return true;
}

task_process_status PortsOrch::setPortAutoNeg(sai_object_id_t id, int an)
task_process_status PortsOrch::setPortAutoNeg(Port &port, bool autoneg)
{
return task_success;
}

bool PortsOrch::setPortFecMode(sai_object_id_t id, int fec)
{
return true;
}

task_process_status PortsOrch::setPortInterfaceType(sai_object_id_t id, sai_port_interface_type_t interface_type)
task_process_status PortsOrch::setPortInterfaceType(Port &port, sai_port_interface_type_t interface_type)
{
return task_success;
}

task_process_status PortsOrch::setPortAdvInterfaceTypes(sai_object_id_t id, std::vector<uint32_t> &interface_types)
task_process_status PortsOrch::setPortAdvInterfaceTypes(Port &port, std::set<sai_port_interface_type_t> &interface_types)
{
return task_success;
}
Expand All @@ -648,21 +638,6 @@ void PortsOrch::getPortSerdesVal(const std::string &s, std::vector<uint32_t> &la
{
}

bool PortsOrch::getPortAdvSpeedsVal(const std::string &s, std::vector<uint32_t> &speed_values)
{
return true;
}

bool PortsOrch::getPortInterfaceTypeVal(const std::string &s, sai_port_interface_type_t &interface_type)
{
return true;
}

bool PortsOrch::getPortAdvInterfaceTypesVal(const std::string &s, std::vector<uint32_t> &type_values)
{
return true;
}

void PortsOrch::removePortSerdesAttribute(sai_object_id_t port_id)
{
}
Expand Down
47 changes: 33 additions & 14 deletions orchagent/port.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
#define SWSS_PORT_H

extern "C" {
#include "sai.h"
#include <sai.h>
}

#include <set>
Expand All @@ -12,6 +12,8 @@ extern "C" {
#include <bitset>
#include <unordered_set>

#include <macaddress.h>

#define DEFAULT_PORT_VLAN_ID 1
/*
* Default MTU is derived from SAI_PORT_ATTR_MTU (1514)
Expand Down Expand Up @@ -73,6 +75,9 @@ struct SystemLagInfo

class Port
{
public:
typedef sai_bridge_port_fdb_learning_mode_t port_learn_mode_t;

public:
enum Type {
CPU,
Expand All @@ -85,14 +90,21 @@ class Port
SUBPORT,
SYSTEM,
UNKNOWN
} ;
};

enum AutoNegMode {
AUTONEG_NOT_SET = -1,
AUTONEG_OFF = 0,
AUTONEG_ON = 1
enum Role
{
Ext, // external
Int, // internal
Inb, // inband
Rec // recirculation
};

public:
static constexpr std::size_t max_lanes = 8; // Max HW lanes
static constexpr std::size_t max_fec_modes = 3; // Max FEC modes (sync with SAI)

public:
Port() {};
Port(std::string alias, Type type) :
m_alias(alias), m_type(type) {};
Expand All @@ -114,12 +126,12 @@ class Port

std::string m_alias;
Type m_type = UNKNOWN;
int m_index = 0; // PHY_PORT: index
uint16_t m_index = 0; // PHY_PORT: index
uint32_t m_mtu = DEFAULT_MTU;
uint32_t m_speed = 0; // Mbps
std::string m_learn_mode = "hardware";
AutoNegMode m_autoneg = Port::AutoNegMode::AUTONEG_NOT_SET;
int m_link_training = -1; // -1 means not set, 0 = disabled, 1 = enabled
port_learn_mode_t m_learn_mode = SAI_BRIDGE_PORT_FDB_LEARNING_MODE_HW;
bool m_autoneg = false;
bool m_link_training = false;
bool m_admin_state_up = false;
bool m_init = false;
bool m_l3_vni = false;
Expand Down Expand Up @@ -154,9 +166,9 @@ class Port
uint32_t m_fdb_count = 0;
uint32_t m_up_member_count = 0;
uint32_t m_maximum_headroom = 0;
std::vector<uint32_t> m_adv_speeds;
std::set<uint32_t> m_adv_speeds;
sai_port_interface_type_t m_interface_type = SAI_PORT_INTERFACE_TYPE_NONE;
std::vector<uint32_t> m_adv_interface_types;
std::set<sai_port_interface_type_t> m_adv_interface_types;
bool m_mpls = false;
/*
* Following bit vector is used to lock
Expand All @@ -181,8 +193,15 @@ class Port
/* pre-emphasis */
std::map<sai_port_serdes_attr_t, std::vector<uint32_t>> m_preemphasis;

bool m_fec_cfg = false;
bool m_an_cfg = false;
/* Force initial parameter configuration flags */
bool m_an_cfg = false; // Auto-negotiation (AN)
bool m_adv_speed_cfg = false; // Advertised speed
bool m_intf_cfg = false; // Interface type
bool m_adv_intf_cfg = false; // Advertised interface type
bool m_fec_cfg = false; // Forward Error Correction (FEC)
bool m_pfc_asym_cfg = false; // Asymmetric Priority Flow Control (PFC)
bool m_lm_cfg = false; // Forwarding Database (FDB) Learning Mode (LM)
bool m_lt_cfg = false; // Link Training (LT)

int m_cap_an = -1; /* Capability - AutoNeg, -1 means not set */
int m_cap_lt = -1; /* Capability - LinkTraining, -1 means not set */
Expand Down
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