[PFCWD + Asym PFC]: Allow PFCWD to detect PFC storm on all priorities when Asym PFC is enabled #1360
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -907,7 +907,7 @@ bool PortsOrch::setPortFec(Port &port, sai_port_fec_mode_t mode) | |
| return true; | ||
| } | ||
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| bool PortsOrch::getPortPfc(sai_object_id_t portId, uint8_t *pfc_tx_bitmask, uint8_t *pfc_rx_bitmask) | ||
| { | ||
| SWSS_LOG_ENTER(); | ||
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@@ -919,12 +919,13 @@ bool PortsOrch::getPortPfc(sai_object_id_t portId, uint8_t *pfc_bitmask) | |
| return false; | ||
| } | ||
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| *pfc_tx_bitmask = p.m_pfc_info.pfc_tx_bitmask; | ||
| *pfc_rx_bitmask = p.m_pfc_info.pfc_rx_bitmask; | ||
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| return true; | ||
| } | ||
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| bool PortsOrch::setPortPfc(sai_object_id_t portId, uint8_t pfc_tx_bitmask, uint8_t pfc_rx_bitmask) | ||
| { | ||
| SWSS_LOG_ENTER(); | ||
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@@ -937,34 +938,60 @@ bool PortsOrch::setPortPfc(sai_object_id_t portId, uint8_t pfc_bitmask) | |
| return false; | ||
| } | ||
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| if (p.m_pfc_info.pfc_mode == SAI_PORT_PRIORITY_FLOW_CONTROL_MODE_COMBINED) | ||
| { | ||
| if (pfc_tx_bitmask != pfc_rx_bitmask) | ||
| { | ||
| SWSS_LOG_ERROR("Cannot set unequal Tx 0x%x and Rx 0x%x PFC bitmasks " | ||
| "for the port 0x%" PRIx64 " with disabled \"asymmetric\" PFC mode", | ||
| pfc_tx_bitmask, pfc_rx_bitmask, portId); | ||
| return false; | ||
| } | ||
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| attr.id = SAI_PORT_ATTR_PRIORITY_FLOW_CONTROL; | ||
| attr.value.u8 = pfc_tx_bitmask; | ||
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| sai_status_t status = sai_port_api->set_port_attribute(portId, &attr); | ||
| if (status != SAI_STATUS_SUCCESS) | ||
| { | ||
| SWSS_LOG_ERROR("Failed to set PFC bitmask 0x%x for the port 0x%" PRIx64 " (rc:%d)", | ||
|
There was a problem hiding this comment. not sure i understand this part. There was a problem hiding this comment. This logic is explained in the "Asymmentric PFC" HLD in the "2.2.1 PortsOrch" section |
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| attr.value.u8, portId, status); | ||
| return false; | ||
| } | ||
| } | ||
| else if (p.m_pfc_info.pfc_mode == SAI_PORT_PRIORITY_FLOW_CONTROL_MODE_SEPARATE) | ||
| { | ||
| attr.id = SAI_PORT_ATTR_PRIORITY_FLOW_CONTROL_TX; | ||
| attr.value.u8 = pfc_tx_bitmask; | ||
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| sai_status_t status = sai_port_api->set_port_attribute(portId, &attr); | ||
| if (status != SAI_STATUS_SUCCESS) | ||
| { | ||
| SWSS_LOG_ERROR("Failed to set Tx PFC bitmask 0x%x for the port 0x%" PRIx64 " (rc:%d)", | ||
| attr.value.u8, portId, status); | ||
| return false; | ||
| } | ||
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| attr.id = SAI_PORT_ATTR_PRIORITY_FLOW_CONTROL_RX; | ||
| attr.value.u8 = pfc_rx_bitmask; | ||
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| status = sai_port_api->set_port_attribute(portId, &attr); | ||
| if (status != SAI_STATUS_SUCCESS) | ||
| { | ||
| SWSS_LOG_ERROR("Failed to set Rx PFC bitmask 0x%x for the port 0x%" PRIx64 " (rc:%d)", | ||
| attr.value.u8, portId, status); | ||
| return false; | ||
| } | ||
| } | ||
| else | ||
| { | ||
| SWSS_LOG_ERROR("Incorrect PFC mode %u for the port 0x%" PRIx64, p.m_pfc_info.pfc_mode, portId); | ||
| return false; | ||
| } | ||
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| p.m_pfc_info.pfc_tx_bitmask = pfc_tx_bitmask; | ||
| p.m_pfc_info.pfc_rx_bitmask = pfc_rx_bitmask; | ||
| m_portList[p.m_alias] = p; | ||
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| return true; | ||
| } | ||
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@@ -974,59 +1001,57 @@ bool PortsOrch::setPortPfcAsym(Port &port, string pfc_asym) | |
| SWSS_LOG_ENTER(); | ||
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| sai_attribute_t attr; | ||
| uint8_t pfc_tx_bitmask = 0; | ||
| uint8_t pfc_rx_bitmask = 0; | ||
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| if (pfc_asym_map.find(pfc_asym) == pfc_asym_map.end()) | ||
| { | ||
| SWSS_LOG_ERROR("Incorrect asymmetric PFC mode: %s", pfc_asym.c_str()); | ||
| return false; | ||
| } | ||
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| if (port.m_pfc_info.pfc_mode == pfc_asym_map[pfc_asym]) | ||
| { | ||
| SWSS_LOG_NOTICE("Asymmetric PFC mode is alredy set to \"%s\" for the port 0x%" PRIx64, | ||
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| pfc_asym.c_str(), port.m_port_id); | ||
| return true; | ||
| } | ||
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| if (!getPortPfc(port.m_port_id, &pfc_tx_bitmask, &pfc_rx_bitmask)) | ||
| { | ||
| return false; | ||
| } | ||
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| if (pfc_asym_map[pfc_asym] == SAI_PORT_PRIORITY_FLOW_CONTROL_MODE_SEPARATE) | ||
| { | ||
| pfc_rx_bitmask = static_cast<uint8_t>(0xff); | ||
| } | ||
| else | ||
| { | ||
| pfc_rx_bitmask = pfc_tx_bitmask; | ||
|
There was a problem hiding this comment. logic has changed, can you elaborate it in the code? There was a problem hiding this comment. Logic is exactly the same but code was refactored according to changes for set/getPortPfc API. |
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| } | ||
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| port.m_pfc_info.pfc_mode = pfc_asym_map[pfc_asym]; | ||
| m_portList[port.m_alias] = port; | ||
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| attr.id = SAI_PORT_ATTR_PRIORITY_FLOW_CONTROL_MODE; | ||
| attr.value.s32 = static_cast<int32_t>(port.m_pfc_info.pfc_mode); | ||
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| sai_status_t status = sai_port_api->set_port_attribute(port.m_port_id, &attr); | ||
| if (status != SAI_STATUS_SUCCESS) | ||
| { | ||
| SWSS_LOG_ERROR("Failed to set PFC mode %d for port 0x%" PRIx64 " (rc:%d)", | ||
| port.m_pfc_info.pfc_mode, port.m_port_id, status); | ||
| return false; | ||
| } | ||
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| if (!setPortPfc(port.m_port_id, pfc_tx_bitmask, pfc_rx_bitmask)) | ||
| { | ||
| return false; | ||
| } | ||
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| SWSS_LOG_INFO("Set asymmetric PFC mode to \"%s\" for the port id 0x%" PRIx64, | ||
| pfc_asym.c_str(), port.m_port_id); | ||
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| return true; | ||
| } | ||
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Why do we need to modify Tx Mask? In any case, its a noop if pfcwd is triggered on a lossy priority because the txMask only contains priorities 3 and 4
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Agree, we don' need it. Fixed to modify only Rx mask.