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adds support for uart 4-wire mode operation and parity generation/checking #141

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19 commits merged into from Apr 14, 2020
Merged

adds support for uart 4-wire mode operation and parity generation/checking #141

19 commits merged into from Apr 14, 2020

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@ghost ghost commented Apr 14, 2020

close #110
to test

wit init workspaceuart -a git@github.com:kritikbhimani/block-spi-sifive::block-uart-sifive -a git@github.com:sifive/environment-example-sifive
cd workspaceuart/
wake --init .
wake -v -x 'runSimWith uartDUT VCS'

note: use your respective environment

kritik bhimani added 19 commits April 9, 2020 17:35
 since it will be very rarely used it is added as a
 configuration time feature
…me only configured databits for parity calculation

previously the assumption was to transmit 0x12 user will write 0x12 and not 0x112 in 8bit data mode
@ghost ghost merged commit 9315e2c into sifive:master Apr 14, 2020
terpstra added a commit that referenced this pull request May 4, 2020
This broke tests in a larger repository.
This changed came in PR #141, but do not seem necessary.
terpstra added a commit that referenced this pull request May 4, 2020
This broke tests in a larger repository.
This changed came in PR #141, but do not seem necessary.
This pull request was closed.
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