Update linux kernel for hw-mgmt V.7.0020.4104 (sonic-net#305)

* Update linux kernel for hw-mgmt V.7.0020.4104 * Update kernel configuration Signed-off-by: Stephen Sun <stephens@nvidia.com> * Update kconfig Signed-off-by: Stephen Sun <stephens@nvidia.com> * Remove ACPI and ARCH_SUPPORTS_ACPI because they will be 'y' according to the dependencies Signed-off-by: Stephen Sun <stephens@nvidia.com> --------- Signed-off-by: Stephen Sun <stephens@nvidia.com>
shanshri · Feb 9, 2023 · 464d2cd · 464d2cd
1 parent 6daddcf
commit 464d2cd
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Showing 16 changed files with 1,639 additions and 23 deletions.
diff --git a/patch/0056-platform-x86-mlx-platform-Add-initial-support-f.patch b/patch/0056-platform-x86-mlx-platform-Add-initial-support-f.patch
@@ -1,7 +1,8 @@
+From 1fe47720483933d41d480ae51c3487a2f34e6e1a Mon Sep 17 00:00:00 2001
 From: Vadim Pasternak <vadimp@nvidia.com>
 Date: Mon, 12 Jul 2021 16:39:11 +0000
-Subject: 0056 platform/x86: mlx-platform: Add initial support
- for new modular system
+Subject: [PATCH backport for v5.10 56/97] platform/x86: mlx-platform: Add
+ initial support for new modular system
 
 Add initial chassis management support for Nvidia modular Ethernet
 switch systems MSN4800, providing a high performance switching solution
@@ -33,8 +34,7 @@ line card. The line cards are hot-pluggable.
 
 Line cards are connected to the chassis through I2C interface for the
 chassis management operations and through PCIe for the networking
-operations. Future line cards could be connected to the chassis through
-InfiniBand fabric, instead of PCIe.
+operations.
 
 The first type of line card supports 16x100GbE QSFP28 Ethernet ports.
 Those line cards equipped with the programmable devices aimed for
@@ -2884,5 +2884,5 @@ index 8bce3da32a42..6d14eb3dab50 100644
  		.callback = mlxplat_dmi_msn274x_matched,
  		.matches = {
 -- 
-2.17.1
+2.20.1
 
diff --git a/patch/0157-platform-x86-mlx-platform-Make-activation-of-some-dr.patch b/patch/0157-platform-x86-mlx-platform-Make-activation-of-some-dr.patch
@@ -0,0 +1,120 @@
+From b384a287a5732f7ea3b6e0b13b1aa6ba0d70c440 Mon Sep 17 00:00:00 2001
+From: Vadim Pasternak <vadimp@nvidia.com>
+Date: Mon, 14 Feb 2022 09:46:16 +0200
+Subject: [PATCH platform-next 1/8] platform/x86: mlx-platform: Make activation
+ of some drivers conditional
+
+Current assumption in driver that any system is capable of LED,
+hotplug or watchdog support. It could be not true for some new coming
+systems.
+Add validation for LED, hotplug, watchdog configuration and skip
+activation of relevant drivers if not configured.
+
+Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
+---
+ drivers/platform/x86/mlx-platform.c | 62 ++++++++++++++++-------------
+ 1 file changed, 35 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
+index fac4b6dcf..e0a35412f 100644
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -5206,16 +5206,18 @@ static int __init mlxplat_init(void)
+ 	}
+
+ 	/* Add hotplug driver */
+-	mlxplat_hotplug->regmap = priv->regmap;
+-	priv->pdev_hotplug = platform_device_register_resndata(
+-				&mlxplat_dev->dev, "mlxreg-hotplug",
+-				PLATFORM_DEVID_NONE,
+-				mlxplat_mlxcpld_resources,
+-				ARRAY_SIZE(mlxplat_mlxcpld_resources),
+-				mlxplat_hotplug, sizeof(*mlxplat_hotplug));
+-	if (IS_ERR(priv->pdev_hotplug)) {
+-		err = PTR_ERR(priv->pdev_hotplug);
+-		goto fail_platform_mux_register;
++	if (mlxplat_hotplug) {
++		mlxplat_hotplug->regmap = priv->regmap;
++		priv->pdev_hotplug =
++		platform_device_register_resndata(&mlxplat_dev->dev,
++						  "mlxreg-hotplug", PLATFORM_DEVID_NONE,
++						  mlxplat_mlxcpld_resources,
++						  ARRAY_SIZE(mlxplat_mlxcpld_resources),
++						  mlxplat_hotplug, sizeof(*mlxplat_hotplug));
++		if (IS_ERR(priv->pdev_hotplug)) {
++			err = PTR_ERR(priv->pdev_hotplug);
++			goto fail_platform_mux_register;
++		}
+ 	}
+
+ 	/* Set default registers. */
+@@ -5228,24 +5230,26 @@ static int __init mlxplat_init(void)
+ 	}
+
+ 	/* Add LED driver. */
+-	mlxplat_led->regmap = priv->regmap;
+-	priv->pdev_led = platform_device_register_resndata(
+-				&mlxplat_dev->dev, "leds-mlxreg",
+-				PLATFORM_DEVID_NONE, NULL, 0,
+-				mlxplat_led, sizeof(*mlxplat_led));
+-	if (IS_ERR(priv->pdev_led)) {
+-		err = PTR_ERR(priv->pdev_led);
+-		goto fail_platform_hotplug_register;
++	if (mlxplat_led) {
++		mlxplat_led->regmap = priv->regmap;
++		priv->pdev_led =
++		platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg",
++						  PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led,
++						  sizeof(*mlxplat_led));
++		if (IS_ERR(priv->pdev_led)) {
++			err = PTR_ERR(priv->pdev_led);
++			goto fail_platform_hotplug_register;
++		}
+ 	}
+
+ 	/* Add registers io access driver. */
+ 	if (mlxplat_regs_io) {
+ 		mlxplat_regs_io->regmap = priv->regmap;
+-		priv->pdev_io_regs = platform_device_register_resndata(
+-					&mlxplat_dev->dev, "mlxreg-io",
+-					PLATFORM_DEVID_NONE, NULL, 0,
+-					mlxplat_regs_io,
+-					sizeof(*mlxplat_regs_io));
++		priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev,
++								       "mlxreg-io",
++								       PLATFORM_DEVID_NONE, NULL,
++								       0, mlxplat_regs_io,
++								       sizeof(*mlxplat_regs_io));
+ 		if (IS_ERR(priv->pdev_io_regs)) {
+ 			err = PTR_ERR(priv->pdev_io_regs);
+ 			goto fail_platform_led_register;
+@@ -5302,9 +5306,11 @@ static int __init mlxplat_init(void)
+ 	if (mlxplat_regs_io)
+ 		platform_device_unregister(priv->pdev_io_regs);
+ fail_platform_led_register:
+-	platform_device_unregister(priv->pdev_led);
++	if (mlxplat_led)
++		platform_device_unregister(priv->pdev_led);
+ fail_platform_hotplug_register:
+-	platform_device_unregister(priv->pdev_hotplug);
++	if (mlxplat_hotplug)
++		platform_device_unregister(priv->pdev_hotplug);
+ fail_platform_mux_register:
+ 	while (--i >= 0)
+ 		platform_device_unregister(priv->pdev_mux[i]);
+@@ -5327,8 +5333,10 @@ static void __exit mlxplat_exit(void)
+ 		platform_device_unregister(priv->pdev_fan);
+ 	if (priv->pdev_io_regs)
+ 		platform_device_unregister(priv->pdev_io_regs);
+-	platform_device_unregister(priv->pdev_led);
+-	platform_device_unregister(priv->pdev_hotplug);
++	if (priv->pdev_led)
++		platform_device_unregister(priv->pdev_led);
++	if (priv->pdev_hotplug)
++		platform_device_unregister(priv->pdev_hotplug);
+
+ 	for (i = mlxplat_mux_num - 1; i >= 0 ; i--)
+ 		platform_device_unregister(priv->pdev_mux[i]);
+-- 
+2.20.1
+
diff --git a/patch/0158-platform-x86-mlx-platform-Add-cosmetic-changes-for-a.patch b/patch/0158-platform-x86-mlx-platform-Add-cosmetic-changes-for-a.patch
@@ -0,0 +1,84 @@
+From cd26dadb7e9c5eedb4e24cd60d4de1cda0e8f889 Mon Sep 17 00:00:00 2001
+From: Vadim Pasternak <vadimp@nvidia.com>
+Date: Mon, 14 Feb 2022 10:07:11 +0200
+Subject: [PATCH platform-next 2/8] platform/x86: mlx-platform: Add cosmetic
+ changes for alignment
+
+Align the first argument with open parenthesis for
+platform_device_register_resndata() calls.
+
+Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
+---
+ drivers/platform/x86/mlx-platform.c | 36 +++++++++++++----------------
+ 1 file changed, 16 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
+index e0a35412f..a74fcd9d1 100644
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -5183,22 +5183,20 @@ static int __init mlxplat_init(void)
+ 	nr = (nr == mlxplat_max_adap_num) ? -1 : nr;
+ 	if (mlxplat_i2c)
+ 		mlxplat_i2c->regmap = priv->regmap;
+-	priv->pdev_i2c = platform_device_register_resndata(
+-					&mlxplat_dev->dev, "i2c_mlxcpld",
+-					nr, mlxplat_mlxcpld_resources,
+-					ARRAY_SIZE(mlxplat_mlxcpld_resources),
+-					mlxplat_i2c, sizeof(*mlxplat_i2c));
++	priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld",
++							   nr, mlxplat_mlxcpld_resources,
++							   ARRAY_SIZE(mlxplat_mlxcpld_resources),
++							   mlxplat_i2c, sizeof(*mlxplat_i2c));
+ 	if (IS_ERR(priv->pdev_i2c)) {
+ 		err = PTR_ERR(priv->pdev_i2c);
+ 		goto fail_alloc;
+ 	}
+
+ 	for (i = 0; i < mlxplat_mux_num; i++) {
+-		priv->pdev_mux[i] = platform_device_register_resndata(
+-						&priv->pdev_i2c->dev,
+-						"i2c-mux-reg", i, NULL,
+-						0, &mlxplat_mux_data[i],
+-						sizeof(mlxplat_mux_data[i]));
++		priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev,
++								      "i2c-mux-reg", i, NULL, 0,
++								      &mlxplat_mux_data[i],
++								      sizeof(mlxplat_mux_data[i]));
+ 		if (IS_ERR(priv->pdev_mux[i])) {
+ 			err = PTR_ERR(priv->pdev_mux[i]);
+ 			goto fail_platform_mux_register;
+@@ -5259,11 +5257,10 @@ static int __init mlxplat_init(void)
+ 	/* Add FAN driver. */
+ 	if (mlxplat_fan) {
+ 		mlxplat_fan->regmap = priv->regmap;
+-		priv->pdev_fan = platform_device_register_resndata(
+-					&mlxplat_dev->dev, "mlxreg-fan",
+-					PLATFORM_DEVID_NONE, NULL, 0,
+-					mlxplat_fan,
+-					sizeof(*mlxplat_fan));
++		priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan",
++								   PLATFORM_DEVID_NONE, NULL, 0,
++								   mlxplat_fan,
++								   sizeof(*mlxplat_fan));
+ 		if (IS_ERR(priv->pdev_fan)) {
+ 			err = PTR_ERR(priv->pdev_fan);
+ 			goto fail_platform_io_regs_register;
+@@ -5277,11 +5274,10 @@ static int __init mlxplat_init(void)
+ 	for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) {
+ 		if (mlxplat_wd_data[j]) {
+ 			mlxplat_wd_data[j]->regmap = priv->regmap;
+-			priv->pdev_wd[j] = platform_device_register_resndata(
+-						&mlxplat_dev->dev, "mlx-wdt",
+-						j, NULL, 0,
+-						mlxplat_wd_data[j],
+-						sizeof(*mlxplat_wd_data[j]));
++			priv->pdev_wd[j] =
++				platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", j,
++								  NULL, 0, mlxplat_wd_data[j],
++								  sizeof(*mlxplat_wd_data[j]));
+ 			if (IS_ERR(priv->pdev_wd[j])) {
+ 				err = PTR_ERR(priv->pdev_wd[j]);
+ 				goto fail_platform_wd_register;
+-- 
+2.20.1
+
diff --git a/patch/0159-mlx-platform-Add-support-for-systems-equipped-with-t.patch b/patch/0159-mlx-platform-Add-support-for-systems-equipped-with-t.patch
@@ -0,0 +1,155 @@
+From a16c819d0896932ca52006fc0ba1c977bd2ad7f6 Mon Sep 17 00:00:00 2001
+From: Vadim Pasternak <vadimp@nvidia.com>
+Date: Wed, 26 Jan 2022 17:16:26 +0200
+Subject: [PATCH platform backport v5.10 03/10] mlx-platform: Add support for
+ systems equipped with two ASICs
+
+Motivation is to support new systems equipped with two ASICs.
+
+Extend driver with:
+- The second ASIC health event.
+- Per ASIC reset control, triggering reset of ASIC internal resources
+  and restarting ASIC initialization flow.
+
+Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
+Reviewed-by: Oleksandr Shamray <oleksandrs@nvidia.com>
+---
+ drivers/platform/x86/mlx-platform.c | 52 ++++++++++++++++++++++++++++-
+ 1 file changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
+index a74fcd9d1..cbe9eab34 100644
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -34,6 +34,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET	0x09
+ #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET	0x0a
+ #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET	0x0b
++#define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET	0x19
+ #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET	0x1c
+ #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET	0x1d
+ #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET	0x1e
+@@ -69,6 +70,9 @@
+ #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
+ #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET	0x51
+ #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET	0x52
++#define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53
++#define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET	0x54
++#define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET	0x55
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET	0x56
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET	0x57
+ #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET		0x58
+@@ -193,6 +197,7 @@
+ 					 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \
+ 					 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN)
+ #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW	0xc1
++#define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2	BIT(2)
+ #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C	BIT(6)
+ #define MLXPLAT_CPLD_PSU_MASK		GENMASK(1, 0)
+ #define MLXPLAT_CPLD_PWR_MASK		GENMASK(1, 0)
+@@ -589,6 +594,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = {
+ 	},
+ };
+
++static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = {
++	{
++		.label = "asic2",
++		.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
++		.mask = MLXPLAT_CPLD_ASIC_MASK,
++		.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
++	},
++};
++
+ static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {
+ 	{
+ 		.data = mlxplat_mlxcpld_default_psu_items_data,
+@@ -1252,6 +1266,15 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
+ 		.inversed = 0,
+ 		.health = true,
+ 	},
++	{
++		.data = mlxplat_mlxcpld_default_asic2_items_data,
++		.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
++		.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
++		.mask = MLXPLAT_CPLD_ASIC_MASK,
++		.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data),
++		.inversed = 0,
++		.health = true,
++	}
+ };
+
+ static
+@@ -1261,7 +1284,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
+ 	.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
+ 	.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
+ 	.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
+-	.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
++	.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
+ };
+
+ static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {
+@@ -3075,6 +3098,18 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
+ 		.bit = GENMASK(7, 0),
+ 		.mode = 0444,
+ 	},
++	{
++		.label = "asic_reset",
++		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
++		.mask = GENMASK(7, 0) & ~BIT(3),
++		.mode = 0644,
++	},
++	{
++		.label = "asic2_reset",
++		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
++		.mask = GENMASK(7, 0) & ~BIT(2),
++		.mode = 0444,
++	},
+ 	{
+ 		.label = "reset_long_pb",
+ 		.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+@@ -3214,6 +3249,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
+ 		.bit = 1,
+ 		.mode = 0444,
+ 	},
++	{
++		.label = "asic2_health",
++		.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
++		.mask = MLXPLAT_CPLD_ASIC_MASK,
++		.bit = 1,
++		.mode = 0444,
++	},
+ 	{
+ 		.label = "fan_dir",
+ 		.reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
+@@ -4254,6 +4296,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ 	case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
++	case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
++	case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
+@@ -4346,6 +4390,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
+ 	case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
++	case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:
++	case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
++	case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -4473,6 +4520,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
+ 	case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
++	case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:
++	case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
++	case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ 	case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+-- 
+2.20.1
+