rvgpu: 添加Special Registers的描述

rvgpu · Nov 22, 2024 · 61ccc96 · 61ccc96
1 parent 4ab1f4c
commit 61ccc96
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Showing 2 changed files with 13 additions and 44 deletions.
diff --git a/llvm/lib/Target/RVGPU/RVGPUIntrinsics.td b/llvm/lib/Target/RVGPU/RVGPUIntrinsics.td
@@ -2520,43 +2520,9 @@ defm isspace_shared_cluster : ISSPACEP<"shared::cluster",
                                        [hasPTX<78>, hasSM<90>]>;
 
 // Special register reads
-def MOV_SPECIAL : RVGPUInst<(outs GPR32:$d),
+def LOAD_SPECIAL : RVGPUInst<(outs GPR32:$d),
                             (ins SpecialRegs:$r),
-                            "mov.b32 \t$d, $r", []>;
-/*
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg0), (MOV_SPECIAL ENVREG0)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg1), (MOV_SPECIAL ENVREG1)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg2), (MOV_SPECIAL ENVREG2)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg3), (MOV_SPECIAL ENVREG3)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg4), (MOV_SPECIAL ENVREG4)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg5), (MOV_SPECIAL ENVREG5)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg6), (MOV_SPECIAL ENVREG6)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg7), (MOV_SPECIAL ENVREG7)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg8), (MOV_SPECIAL ENVREG8)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg9), (MOV_SPECIAL ENVREG9)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg10), (MOV_SPECIAL ENVREG10)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg11), (MOV_SPECIAL ENVREG11)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg12), (MOV_SPECIAL ENVREG12)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg13), (MOV_SPECIAL ENVREG13)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg14), (MOV_SPECIAL ENVREG14)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg15), (MOV_SPECIAL ENVREG15)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg16), (MOV_SPECIAL ENVREG16)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg17), (MOV_SPECIAL ENVREG17)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg18), (MOV_SPECIAL ENVREG18)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg19), (MOV_SPECIAL ENVREG19)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg20), (MOV_SPECIAL ENVREG20)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg21), (MOV_SPECIAL ENVREG21)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg22), (MOV_SPECIAL ENVREG22)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg23), (MOV_SPECIAL ENVREG23)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg24), (MOV_SPECIAL ENVREG24)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg25), (MOV_SPECIAL ENVREG25)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg26), (MOV_SPECIAL ENVREG26)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg27), (MOV_SPECIAL ENVREG27)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg28), (MOV_SPECIAL ENVREG28)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg29), (MOV_SPECIAL ENVREG29)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg30), (MOV_SPECIAL ENVREG30)>;
-def : Pat<(int_rvgpu_read_ptx_sreg_envreg31), (MOV_SPECIAL ENVREG31)>;
-*/
+                            "ldsreg.b32 \t$d, $r", []>;
 
 // rotate builtin support
 
@@ -6224,7 +6190,7 @@ class PTX_READ_SREG_R64<string regname, Intrinsic intop, list<Predicate> Preds=[
 
 class PTX_READ_SREG_R32<string regname, Intrinsic intop, list<Predicate> Preds=[]>
   : RVGPUInst<(outs GPR32:$d), (ins),
-              !strconcat("ldsreg \t$d, %", regname, ""),
+              !strconcat("ldsreg \t$d, ", regname, ""),
               [(set GPR32:$d, (intop))]>,
     Requires<Preds>;
 

diff --git a/llvm/lib/Target/RVGPU/RVGPURegisterInfo.td b/llvm/lib/Target/RVGPU/RVGPURegisterInfo.td
@@ -41,7 +41,9 @@ let Namespace = "RVGPU" in {
 //===----------------------------------------------------------------------===//
 //  Helpers
 //===----------------------------------------------------------------------===//
-
+// size为2时，表示64位寄存器：[dr0, dr1, dr2, ... , dr126]
+// size为3时，表示96位寄存器: [tr0, tr1, tr2, ... , tr125]
+// size为4时，表示128位寄存器：[qr0, qr1, qr2, ... , qr124]
 class RegSeqNames<int last_reg, int stride, int size, string prefix, int start = 0> {
   int next = !add(start, stride);
   int end_reg = !add(start, size, -1);
@@ -172,7 +174,6 @@ def VReg96 : RVGPURegisterTuples<[sub0, sub1, sub2], GPR32, 127, 1, 3, "tr">;
 // GPR 128-bit registers
 def VReg128 : RVGPURegisterTuples<[sub0, sub1, sub2, sub3], GPR32, 127, 1, 4, "qr">;
 
-
 // Register class for all vector registers (VGPRs + Interpolation Registers)
 class RegClassBase<int numRegs, list<ValueType> regTypes, dag regList> :
     RVGPURegClass<regTypes, 32, regList> {
@@ -207,15 +208,17 @@ defm GPR128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], (add VReg
 // 定义1个Predicate Register
 def PREG : RVGPUReg<"%p">;
 
-// 定义 GR0 ~ GR127，共128个32位的通用寄存器
-foreach i = 0...31 in {
-  def ENVREG#i : RVGPUReg<"%sreg"#i>;
-}
+// 定义Special Registers
+def SREG0 : RVGPUReg<"tid.x">;
+def SREG1 : RVGPUReg<"tid.y">;
+def SREG2 : RVGPUReg<"tid.z">;
+def SREG3 : RVGPUReg<"tid.w">;
+
 
 //===----------------------------------------------------------------------===//
 //  Register classes: 为128个通用寄存器定义
 //===----------------------------------------------------------------------===//
 def Int1Regs : RVGPURegClass<[i1], 32, (add PREG)>;
 
 // Read RVGPURegisterInfo.cpp to see how VRFrame and VRDepot are used.
-def SpecialRegs : RVGPURegClass<[i32], 32, (add (sequence "ENVREG%u", 0, 31))>;
+def SpecialRegs : RVGPURegClass<[i32], 32, (add (sequence "SREG%u", 0, 3))>;