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More RISC-V instructions in core::arch #1271

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Jan 5, 2022
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2 changes: 2 additions & 0 deletions crates/core_arch/src/core_arch_docs.md
Original file line number Diff line number Diff line change
Expand Up @@ -186,6 +186,7 @@ others at:
* [`arm`]
* [`aarch64`]
* [`riscv`]
* [`riscv64`]
* [`mips`]
* [`mips64`]
* [`powerpc`]
Expand All @@ -198,6 +199,7 @@ others at:
[`arm`]: arm/index.html
[`aarch64`]: aarch64/index.html
[`riscv`]: riscv/index.html
[`riscv64`]: riscv64/index.html
[`mips`]: mips/index.html
[`mips64`]: mips64/index.html
[`powerpc`]: powerpc/index.html
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15 changes: 15 additions & 0 deletions crates/core_arch/src/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,17 @@ pub mod arch {
pub use crate::core_arch::riscv::*;
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}

/// Platform-specific intrinsics for the `riscv64` platform.
///
/// See the [module documentation](../index.html) for more details.
#[cfg(any(target_arch = "riscv64", doc))]
#[doc(cfg(any(target_arch = "riscv64")))]
#[unstable(feature = "stdsimd", issue = "27731")]
pub mod riscv64 {
pub use crate::core_arch::riscv::*;
pub use crate::core_arch::riscv64::*;
}

/// Platform-specific intrinsics for the `wasm32` platform.
///
/// This module provides intrinsics specific to the WebAssembly
Expand Down Expand Up @@ -266,6 +277,10 @@ mod arm;
#[doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64")))]
mod riscv;

#[cfg(any(target_arch = "riscv64", doc))]
#[doc(cfg(any(target_arch = "riscv64")))]
mod riscv64;

#[cfg(any(target_family = "wasm", doc))]
#[doc(cfg(target_family = "wasm"))]
mod wasm32;
Expand Down
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