More RISC-V instructions in core::arch

crates/core_arch/src/core_arch_docs.md

@@ -185,7 +185,8 @@ others at:
 * [`x86_64`]
 * [`arm`]
 * [`aarch64`]
-* [`riscv`]
+* [`riscv32`]
+* [`riscv64`]
 * [`mips`]
 * [`mips64`]
 * [`powerpc`]
@@ -197,7 +198,8 @@ others at:
 [`x86_64`]: x86_64/index.html
 [`arm`]: arm/index.html
 [`aarch64`]: aarch64/index.html
-[`riscv`]: riscv/index.html
+[`riscv32`]: riscv32/index.html
+[`riscv64`]: riscv64/index.html
 [`mips`]: mips/index.html
 [`mips64`]: mips64/index.html
 [`powerpc`]: powerpc/index.html

crates/core_arch/src/mod.rs

@@ -56,14 +56,28 @@ pub mod arch {
         pub use crate::core_arch::aarch64::*;
     }
 
-    /// Platform-specific intrinsics for the `riscv` platform.
+    /// Platform-specific intrinsics for the `riscv32` platform.
     ///
     /// See the [module documentation](../index.html) for more details.
-    #[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
-    #[doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64")))]
+    #[cfg(any(target_arch = "riscv32", doc))]
+    #[doc(cfg(any(target_arch = "riscv32")))]
     #[unstable(feature = "stdsimd", issue = "27731")]
-    pub mod riscv {
-        pub use crate::core_arch::riscv::*;
+    pub mod riscv32 {
+        pub use crate::core_arch::riscv_shared::*;
+    }
+
+    /// Platform-specific intrinsics for the `riscv64` platform.
+    ///
+    /// See the [module documentation](../index.html) for more details.
+    #[cfg(any(target_arch = "riscv64", doc))]
+    #[doc(cfg(any(target_arch = "riscv64")))]
+    #[unstable(feature = "stdsimd", issue = "27731")]
+    pub mod riscv64 {
+        pub use crate::core_arch::riscv64::*;
+        // RISC-V RV64 supports all RV32 instructions as well in current specifications (2022-01-05).
+        // Module `riscv_shared` includes instructions available under all RISC-V platforms,
+        // i.e. RISC-V RV32 instructions.
+        pub use crate::core_arch::riscv_shared::*;
     }
 
     /// Platform-specific intrinsics for the `wasm32` platform.
@@ -264,7 +278,11 @@ mod arm;
 
 #[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
 #[doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64")))]
-mod riscv;
+mod riscv_shared;
+
+#[cfg(any(target_arch = "riscv64", doc))]
+#[doc(cfg(any(target_arch = "riscv64")))]
+mod riscv64;
 
 #[cfg(any(target_family = "wasm", doc))]
 #[doc(cfg(target_family = "wasm"))]

crates/core_arch/src/riscv64/mod.rs

@@ -0,0 +1,49 @@
+//! RISC-V RV64 specific intrinsics
+use crate::arch::asm;
+
+/// Loads virtual machine memory by unsigned word integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// This operation is not available under RV32 base instruction set.
+///
+/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.WU`
+/// instruction which is effectively an unreference to any memory address.
+#[inline]
+pub unsafe fn hlv_wu(src: *const u32) -> u32 {
+    let value: u32;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x681", out(reg) value, in(reg) src, options(readonly, nostack));
+    value
+}
+
+/// Loads virtual machine memory by unsigned double integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// This operation is not available under RV32 base instruction set.
+///
+/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.D`
+/// instruction which is effectively an unreference to any memory address.
+#[inline]
+pub unsafe fn hlv_d(src: *const i64) -> i64 {
+    let value: i64;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x6C0", out(reg) value, in(reg) src, options(readonly, nostack));
+    value
+}
+
+/// Stores virtual machine memory by double integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// This function is unsafe for it accesses the virtual supervisor or user via a `HSV.D`
+/// instruction which is effectively an unreference to any memory address.
+#[inline]
+pub unsafe fn hsv_d(dst: *mut i64, src: i64) {
+    asm!(".insn r 0x73, 0x4, 0x37, x0, {}, {}", in(reg) dst, in(reg) src, options(nostack));
+}