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correct names of instructions
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SparrowLii committed Mar 9, 2021
1 parent 99c0d23 commit 4ad071a
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Showing 3 changed files with 19 additions and 18 deletions.
32 changes: 16 additions & 16 deletions crates/core_arch/src/aarch64/neon/generated.rs
Original file line number Diff line number Diff line change
Expand Up @@ -800,7 +800,7 @@ pub unsafe fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t {
/// Compare signed less than or equal to zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmle))]
#[cfg_attr(test, assert_instr(cmge))]
pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t {
let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
simd_le(a, transmute(b))
Expand All @@ -809,7 +809,7 @@ pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t {
/// Compare signed less than or equal to zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmle))]
#[cfg_attr(test, assert_instr(cmge))]
pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
simd_le(a, transmute(b))
Expand All @@ -818,7 +818,7 @@ pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
/// Compare signed less than or equal to zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmle))]
#[cfg_attr(test, assert_instr(cmge))]
pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t {
let b: i16x4 = i16x4::new(0, 0, 0, 0);
simd_le(a, transmute(b))
Expand All @@ -827,7 +827,7 @@ pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t {
/// Compare signed less than or equal to zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmle))]
#[cfg_attr(test, assert_instr(cmge))]
pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
simd_le(a, transmute(b))
Expand All @@ -836,7 +836,7 @@ pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
/// Compare signed less than or equal to zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmle))]
#[cfg_attr(test, assert_instr(cmge))]
pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t {
let b: i32x2 = i32x2::new(0, 0);
simd_le(a, transmute(b))
Expand All @@ -845,7 +845,7 @@ pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t {
/// Compare signed less than or equal to zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmle))]
#[cfg_attr(test, assert_instr(cmge))]
pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
let b: i32x4 = i32x4::new(0, 0, 0, 0);
simd_le(a, transmute(b))
Expand All @@ -854,7 +854,7 @@ pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
/// Compare signed less than or equal to zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmle))]
#[cfg_attr(test, assert_instr(cmge))]
pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t {
let b: i64x1 = i64x1::new(0);
simd_le(a, transmute(b))
Expand All @@ -863,7 +863,7 @@ pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t {
/// Compare signed less than or equal to zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmle))]
#[cfg_attr(test, assert_instr(cmge))]
pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t {
let b: i64x2 = i64x2::new(0, 0);
simd_le(a, transmute(b))
Expand Down Expand Up @@ -908,7 +908,7 @@ pub unsafe fn vclezq_f64(a: float64x2_t) -> uint64x2_t {
/// Compare signed less than zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmlt))]
#[cfg_attr(test, assert_instr(cmgt))]
pub unsafe fn vcltz_s8(a: int8x8_t) -> uint8x8_t {
let b: i8x8 = i8x8::new(7, 7, 7, 7, 7, 7, 7, 7);
let c: int8x8_t = simd_shr(a, transmute(b));
Expand All @@ -918,7 +918,7 @@ pub unsafe fn vcltz_s8(a: int8x8_t) -> uint8x8_t {
/// Compare signed less than zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmlt))]
#[cfg_attr(test, assert_instr(cmgt))]
pub unsafe fn vcltzq_s8(a: int8x16_t) -> uint8x16_t {
let b: i8x16 = i8x16::new(7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7);
let c: int8x16_t = simd_shr(a, transmute(b));
Expand All @@ -928,7 +928,7 @@ pub unsafe fn vcltzq_s8(a: int8x16_t) -> uint8x16_t {
/// Compare signed less than zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmlt))]
#[cfg_attr(test, assert_instr(cmgt))]
pub unsafe fn vcltz_s16(a: int16x4_t) -> uint16x4_t {
let b: i16x4 = i16x4::new(15, 15, 15, 15);
let c: int16x4_t = simd_shr(a, transmute(b));
Expand All @@ -938,7 +938,7 @@ pub unsafe fn vcltz_s16(a: int16x4_t) -> uint16x4_t {
/// Compare signed less than zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmlt))]
#[cfg_attr(test, assert_instr(cmgt))]
pub unsafe fn vcltzq_s16(a: int16x8_t) -> uint16x8_t {
let b: i16x8 = i16x8::new(15, 15, 15, 15, 15, 15, 15, 15);
let c: int16x8_t = simd_shr(a, transmute(b));
Expand All @@ -948,7 +948,7 @@ pub unsafe fn vcltzq_s16(a: int16x8_t) -> uint16x8_t {
/// Compare signed less than zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmlt))]
#[cfg_attr(test, assert_instr(cmgt))]
pub unsafe fn vcltz_s32(a: int32x2_t) -> uint32x2_t {
let b: i32x2 = i32x2::new(31, 31);
let c: int32x2_t = simd_shr(a, transmute(b));
Expand All @@ -958,7 +958,7 @@ pub unsafe fn vcltz_s32(a: int32x2_t) -> uint32x2_t {
/// Compare signed less than zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmlt))]
#[cfg_attr(test, assert_instr(cmgt))]
pub unsafe fn vcltzq_s32(a: int32x4_t) -> uint32x4_t {
let b: i32x4 = i32x4::new(31, 31, 31, 31);
let c: int32x4_t = simd_shr(a, transmute(b));
Expand All @@ -968,7 +968,7 @@ pub unsafe fn vcltzq_s32(a: int32x4_t) -> uint32x4_t {
/// Compare signed less than zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmlt))]
#[cfg_attr(test, assert_instr(cmgt))]
pub unsafe fn vcltz_s64(a: int64x1_t) -> uint64x1_t {
let b: i64x1 = i64x1::new(63);
let c: int64x1_t = simd_shr(a, transmute(b));
Expand All @@ -978,7 +978,7 @@ pub unsafe fn vcltz_s64(a: int64x1_t) -> uint64x1_t {
/// Compare signed less than zero
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(cmlt))]
#[cfg_attr(test, assert_instr(cmgt))]
pub unsafe fn vcltzq_s64(a: int64x2_t) -> uint64x2_t {
let b: i64x2 = i64x2::new(63, 63);
let c: int64x2_t = simd_shr(a, transmute(b));
Expand Down
4 changes: 2 additions & 2 deletions crates/stdarch-gen/neon.spec
Original file line number Diff line number Diff line change
Expand Up @@ -475,7 +475,7 @@ a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0
fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
validate TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE

aarch64 = cmle
aarch64 = cmge
generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t

/// Floating-point compare less than or equal to zero
Expand All @@ -497,7 +497,7 @@ a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0
fixed = BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1
validate TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE

aarch64 = cmlt
aarch64 = cmgt
generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t

/// Floating-point compare less than zero
Expand Down
1 change: 1 addition & 0 deletions crates/stdarch-gen/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -999,6 +999,7 @@ mod test {
let mut file_arm = File::create(arm_out_path.join(ARM_OUT))?;
file_arm.write_all(out_arm.as_bytes())?;
file_arm.write_all(tests_arm.as_bytes())?;

let aarch64_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap())
.join("src")
.join("aarch64")
Expand Down

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