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[MIR] Requiring TempRef to only be assigned to once may be too restrictive #31002
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Another option would be to convert these temporaries into lvalues (i.e. variables). Could it be that the unfinished |
I am confused. We do not require temps to be SSA, either in Mir or trans... But in trans we optimize in those cases where we can (I.e., where temps are SSA). Right? |
@nikomatsakis this comment suggests they are SSA with borrowing and mutation possible. Might be me misinterpreting what SSA means, but what I mean is that these are not supposed to be assigned more than once, for some definitions of once. |
@nagisa I see. Yes, ok, I agree that comment was in error. I think though that you probably ought to update it in #31077 :) I would still expect temps to be "DSA" -- which afaik I just made up -- that is, no two writes can reach one another without exiting the "live scope" of the temporary, but I don't know that it's an important property. FWIW I think SSA usually implies that values are "pure values", i.e., you can't take their address and mutate them. But I know what you mean in any case. |
er, ought to have updated it |
I’ll keep updating the comment in mind in whatever PR that comes next. |
In MIR we want
tmp*
values to be SSA, however ensuring that constraint in trans (i.e. in TempRef) is wrong, I think.Namely, for code like this:
we will generate following MIR (graphviz version, because easier to visualise):
which will result in
Note how we assign
tmp0
twice, but the two branches are fully disjoint, and thus, for the purposes of data-flowtmp0
is still SSA, but for the purposes of translatortmp0
is assigned multiple times.If we want
TempRef
s to staySSA
across translation of the whole function, we will need something like aphi
in the MIR.cc @nikomatsakis
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