Update tests/ui/abi/riscv32e-registers.rs

Co-authored-by: Jubilee <workingjubilee@gmail.com>
rust-lang · Oct 5, 2024 · a3f6821 · a3f6821
1 parent 2fdda7d
commit a3f6821
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/tests/ui/abi/riscv32e-registers.rs b/tests/ui/abi/riscv32e-registers.rs
@@ -22,8 +22,7 @@ macro_rules! asm {
 #[lang = "sized"]
 trait Sized {}
 
-// Check that loads to registers x1..=x16 will be generated but loads to registers x17..=x31 will
-// not.
+// Verify registers x1..=x15 are addressable on riscv32e, but registers x16..=x31 are not.
 #[no_mangle]
 pub unsafe fn registers() {
     asm!("li x1, 0");