Add cfg to Peripheral fields

The cfg conditional compilation attribute was only set on impl blocks of
peripherals. This commit also sets it on the fields themselves to be
more consistent.

Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>

src/lib.rs

@@ -58,7 +58,7 @@ mod macros;
 
 pub mod asm;
 pub mod interrupt;
-#[cfg(not(armv6m))]
+#[cfg(all(not(armv6m), not(armv8m_base)))]
 pub mod itm;
 pub mod peripheral;
 pub mod register;

src/peripheral/cbp.rs

@@ -1,6 +1,6 @@
 //! Cache and branch predictor maintenance operations
 //!
-//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+//! *NOTE* Not available on Armv6-M.
 
 use volatile_register::WO;
 

src/peripheral/fpb.rs

@@ -1,6 +1,6 @@
 //! Flash Patch and Breakpoint unit
 //!
-//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+//! *NOTE* Not available on Armv6-M.
 
 use volatile_register::{RO, RW, WO};
 

src/peripheral/fpu.rs

@@ -1,6 +1,7 @@
 //! Floating Point Unit
 //!
-//! *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`)
+//! *NOTE* Available only on targets with a Floating Point Unit (FPU) extension. Those are the
+//! targets ending with `hf`.
 
 use volatile_register::{RO, RW};
 

src/peripheral/itm.rs

@@ -1,6 +1,6 @@
 //! Instrumentation Trace Macrocell
 //!
-//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+//! *NOTE* Not available on Armv6-M and Armv8-M Baseline.
 
 use core::cell::UnsafeCell;
 use core::ptr;

src/peripheral/mod.rs

@@ -73,7 +73,7 @@ pub mod fpb;
 // NOTE(target_arch) is for documentation purposes
 #[cfg(any(has_fpu, target_arch = "x86_64"))]
 pub mod fpu;
-#[cfg(not(armv6m))]
+#[cfg(all(not(armv6m), not(armv8m_base)))]
 pub mod itm;
 pub mod mpu;
 pub mod nvic;
@@ -90,7 +90,9 @@ mod test;
 /// Core peripherals
 #[allow(non_snake_case)]
 pub struct Peripherals {
-    /// Cache and branch predictor maintenance operations (not present on Cortex-M0 variants)
+    /// Cache and branch predictor maintenance operations.
+    /// Not available on Armv6-M.
+    #[cfg(not(armv6m))]
     pub CBP: CBP,
 
     /// CPUID
@@ -102,13 +104,19 @@ pub struct Peripherals {
     /// Data Watchpoint and Trace unit
     pub DWT: DWT,
 
-    /// Flash Patch and Breakpoint unit (not present on Cortex-M0 variants)
+    /// Flash Patch and Breakpoint unit.
+    /// Not available on Armv6-M.
+    #[cfg(not(armv6m))]
     pub FPB: FPB,
 
-    /// Floating Point Unit (only present on `thumbv7em-none-eabihf`)
+    /// Floating Point Unit.
+    /// Available only on `hf` targets.
+    #[cfg(any(has_fpu, target_arch = "x86_64"))]
     pub FPU: FPU,
 
-    /// Instrumentation Trace Macrocell (not present on Cortex-M0 variants)
+    /// Instrumentation Trace Macrocell.
+    /// Not available on Armv6-M and Armv8-M Baseline.
+    #[cfg(all(not(armv6m), not(armv8m_base)))]
     pub ITM: ITM,
 
     /// Memory Protection Unit
@@ -123,7 +131,9 @@ pub struct Peripherals {
     /// SysTick: System Timer
     pub SYST: SYST,
 
-    /// Trace Port Interface Unit (not present on Cortex-M0 variants)
+    /// Trace Port Interface Unit.
+    /// Not available on Armv6-M.
+    #[cfg(not(armv6m))]
     pub TPIU: TPIU,
 
     // Private field making `Peripherals` non-exhaustive. We don't use `#[non_exhaustive]` so we
@@ -155,6 +165,7 @@ impl Peripherals {
         CORE_PERIPHERALS = true;
 
         Peripherals {
+            #[cfg(not(armv6m))]
             CBP: CBP {
                 _marker: PhantomData,
             },
@@ -167,12 +178,15 @@ impl Peripherals {
             DWT: DWT {
                 _marker: PhantomData,
             },
+            #[cfg(not(armv6m))]
             FPB: FPB {
                 _marker: PhantomData,
             },
+            #[cfg(any(has_fpu, target_arch = "x86_64"))]
             FPU: FPU {
                 _marker: PhantomData,
             },
+            #[cfg(all(not(armv6m), not(armv8m_base)))]
             ITM: ITM {
                 _marker: PhantomData,
             },
@@ -188,6 +202,7 @@ impl Peripherals {
             SYST: SYST {
                 _marker: PhantomData,
             },
+            #[cfg(not(armv6m))]
             TPIU: TPIU {
                 _marker: PhantomData,
             },
@@ -197,10 +212,12 @@ impl Peripherals {
 }
 
 /// Cache and branch predictor maintenance operations
+#[cfg(not(armv6m))]
 pub struct CBP {
     _marker: PhantomData<*const ()>,
 }
 
+#[cfg(not(armv6m))]
 unsafe impl Send for CBP {}
 
 #[cfg(not(armv6m))]
@@ -302,10 +319,12 @@ impl ops::Deref for DWT {
 }
 
 /// Flash Patch and Breakpoint unit
+#[cfg(not(armv6m))]
 pub struct FPB {
     _marker: PhantomData<*const ()>,
 }
 
+#[cfg(not(armv6m))]
 unsafe impl Send for FPB {}
 
 #[cfg(not(armv6m))]
@@ -328,10 +347,12 @@ impl ops::Deref for FPB {
 }
 
 /// Floating Point Unit
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
 pub struct FPU {
     _marker: PhantomData<*const ()>,
 }
 
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
 unsafe impl Send for FPU {}
 
 #[cfg(any(has_fpu, target_arch = "x86_64"))]
@@ -354,13 +375,15 @@ impl ops::Deref for FPU {
 }
 
 /// Instrumentation Trace Macrocell
+#[cfg(all(not(armv6m), not(armv8m_base)))]
 pub struct ITM {
     _marker: PhantomData<*const ()>,
 }
 
+#[cfg(all(not(armv6m), not(armv8m_base)))]
 unsafe impl Send for ITM {}
 
-#[cfg(not(armv6m))]
+#[cfg(all(not(armv6m), not(armv8m_base)))]
 impl ITM {
     /// Returns a pointer to the register block
     #[inline(always)]
@@ -369,7 +392,7 @@ impl ITM {
     }
 }
 
-#[cfg(not(armv6m))]
+#[cfg(all(not(armv6m), not(armv8m_base)))]
 impl ops::Deref for ITM {
     type Target = self::itm::RegisterBlock;
 
@@ -379,7 +402,7 @@ impl ops::Deref for ITM {
     }
 }
 
-#[cfg(not(armv6m))]
+#[cfg(all(not(armv6m), not(armv8m_base)))]
 impl ops::DerefMut for ITM {
     #[inline(always)]
     fn deref_mut(&mut self) -> &mut Self::Target {
@@ -484,10 +507,12 @@ impl ops::Deref for SYST {
 }
 
 /// Trace Port Interface Unit
+#[cfg(not(armv6m))]
 pub struct TPIU {
     _marker: PhantomData<*const ()>,
 }
 
+#[cfg(not(armv6m))]
 unsafe impl Send for TPIU {}
 
 #[cfg(not(armv6m))]

src/peripheral/tpiu.rs

@@ -1,6 +1,6 @@
 //! Trace Port Interface Unit;
 //!
-//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+//! *NOTE* Not available on Armv6-M.
 
 use volatile_register::{RO, RW, WO};