- Rohan Rajesh Kalbag
- Anubhav Bhatla
Abstract: Often the VLSI design schematic of a system cannot be emulated/verified on a single FPGA, due to the finite number of programmable logic elements present in the FPGA. Interconnections between circuit elements can be conveniently represented using graphs, Logic gates, LUTs, FFs and other entities present in the design can be modelled as graph nodes and the interconnections are modelled as edges, if there are multiple parallel interconnects between two entities, we can represent the same using weighted graphs. Suppose we wish to computerize dividing the design among 2 FPGAs using CAD, we can model the problem as a graph partitioning problem.
Suppose we partition the graph into sets
Thus splitting the components among two FPGAs so as to minimize the cost of interconnects (which can be represented by the quantity cut size) denoted by
Thus, one can use the simple metric ratio cut
A much better cost function can be modelled using co-optimization as well to get the minimization problem
We try to implement graph partitioning algorithms and heuristics like the Kernighan-Lin Algorithm, Clustering Based Heuristic, Hagen Kahng EIG Algorithm and compare, analyse their capability in partitioning a given graph network into two partitions and visualise them using plotting tools of matplotlib
, networkx
libraries of Python
Create a virtual environment (only the first time if the folder
./ee677
is absent) usingpython3 -m venv ee677
To setup the virtual environment open a terminal in the directory and do the following command
source ee677/bin/activate
to activate it.
Then setup pip in the following way
pip install -r requirements.txt
.