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pointer masking support #368

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merged 14 commits into from
Sep 26, 2024
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Add statement on pointer masking

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@andresag01 andresag01 left a comment

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Is this going to work efficiently in hybrid code? i.e. Code that is partially purecap but has some parts still running in Integer Pointer Mode. My understanding is that pointer masking is enabled or disabled in a privilege level using CSRs that can only be read/written from higher privileges.

For example, senvcfg.PMM controls pointer masking for U/VU-mode. Therefore, if a program wants to jump from a piece of code in Capability Pointer Mode to a piece of code in Integer Pointer mode, would it have to also do some sort of supervisor call to enable pointer masking on the way in and disable pointer masking on return back to Capability Pointer Mode?

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the proposal should be updated to

  • use the address including the masked bits for the bounds calculation
  • apply the mask before the actual dereference

and then do something better later for capability mode

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Nit: it's not really the decoding mode that is impacted by pointer masking but rather how the instruction interprets the operands. I've made few suggestions to make it clear that we are referring to the type of operand not the mode we are executing in.

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andresag01 commented Sep 25, 2024

Made a few minor suggestions. Also rebased to resolve conflicts in introduction.adoc

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I still think we should not conflate the CHERI mode with the behaviour of the pointer extension - it only really depends on the type of the operand. Otherwise LGTM.

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jrtc27 commented Sep 25, 2024

I still think we should not conflate the CHERI mode with the behaviour of the pointer extension - it only really depends on the type of the operand

Agreed. This matters in particular for a Zcherihybrid.

tariqkurd-repo and others added 4 commits September 26, 2024 17:44
Co-authored-by: Alexander Richardson <mail@alexrichardson.me>
Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
Co-authored-by: Alexander Richardson <mail@alexrichardson.me>
Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
Co-authored-by: Andres Amaya Garcia <andres.amaya@codasip.com>
Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
Co-authored-by: Andres Amaya Garcia <andres.amaya@codasip.com>
Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
Co-authored-by: Alexander Richardson <mail@alexrichardson.me>
Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
@arichardson arichardson merged commit 008e92b into riscv:main Sep 26, 2024
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tariqkurd-repo added a commit to tariqkurd-repo/riscv-cheri that referenced this pull request Oct 9, 2024
Fixes: riscv#360
Co-authored-by: Alexander Richardson <alexrichardson@google.com>
Co-authored-by: Andres Amaya Garcia <andres.amaya@codasip.com>
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5 participants