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swap sense of M-bit, so that 0 is cap mode #305

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merged 4 commits into from
Jul 3, 2024

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it makes more sense for zero to mean cap mode, as it's the same as not having hybrid mode

@tariqkurd-repo tariqkurd-repo requested review from arichardson, andresag01 and jrtc27 and removed request for arichardson July 2, 2024 09:34
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fixes #303

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One minor suggestion otherwise LGTM.

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Co-authored-by: Alexander Richardson <mail@alexrichardson.me>
Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
@arichardson arichardson merged commit 74f05ec into riscv:main Jul 3, 2024
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tariqkurd-repo added a commit to tariqkurd-repo/riscv-cheri that referenced this pull request Oct 9, 2024
It makes more sense for zero to mean cap mode, as it's the same as not
having hybrid mode.

Fixes riscv#303

Co-authored-by: Alexander Richardson <mail@alexrichardson.me>
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2 participants