Indicate that GPRs have tag cleared on reset

src/introduction.adoc

@@ -67,7 +67,7 @@ will result in a hardware exception.
 CHERI capabilities may be held in registers or in memories, and are loaded,
 stored, and dereferenced using CHERI-aware instructions that expect capability
 operands rather than integer addresses. On hardware reset, initial capabilities
-are made available to software via special and general-purpose capability
+are made available to software via capability
 registers. All other capabilities will be derived from these initial valid
 capabilities through valid capability transformations.
 

src/riscv-integration.adoc

@@ -39,6 +39,10 @@ of the capability in an unprivileged register while the *c* notation is used
 to refer to the full capability (i.e. address, metadata and tag) held in the
 same unprivileged register.
 
+The tag of the unprivileged *c* registers must be reset to zero. The reset
+values of the metadata and address fields are UNSPECIFIED for all unprivileged
+*c* registers except *c0*.
+
 Register *c0* is hardwired with all bits, including the capability metadata and
 tag, equal to 0. In other words, *c0* is hardwired to the <<null-cap>>
 capability.