Made spelling of pseudoinstruction and pseudocode consistent (#479)

src/cap-description.adoc

@@ -400,7 +400,7 @@ uses a floating point representation to encode the bounds relative to the
 capability address. The base and top addresses from the bounds are decoded as
 shown below.
 
-WARNING: #TODO: The pseudo-code below does not have a formal notation. It is
+WARNING: #TODO: The pseudocode below does not have a formal notation. It is
 simply a place-holder while the Sail implementation is unavailable. In this
 notation, / means "integer division", [] are the bit-select operators, and
 arithmetic is signed.#

src/insns/cbld_32bit.adoc

@@ -41,7 +41,7 @@ capabilities from integer values.
 
 NOTE: When `cs1` is `c0` this will copy `cs2` to `cd` and clear `cd.tag`.
 However this may change in future extensions, and so software should not
-assume `cs1==0` to be a pseudo instruction for tag clearing.
+assume `cs1==0` to be a pseudoinstruction for tag clearing.
 
 Exceptions::
 include::require_cre.adoc[]

src/insns/csrrw_32bit.adoc

@@ -35,7 +35,7 @@ CSRRW writes `rs1` to extended CSRs in {cheri_int_mode_name}, and reads the addr
 If `cd` is `c0` (or `rd` is `x0`), then the instruction shall not read the CSR
 and shall not cause any of the side effects that might occur on a CSR read.
 +
-The assembler pseudo-instruction to write a capability CSR in {cheri_cap_mode_name},
+The assembler pseudoinstruction to write a capability CSR in {cheri_cap_mode_name},
 `csrw csr, cs1`, is encoded as `csrrw c0, csr, cs1`.
 +
 Access to XLEN-wide CSRs from other extensions is as specified by RISC-V.

src/insns/dret.adoc

@@ -17,7 +17,7 @@ Description::
 <<pcc>>.
 
 NOTE: The <<DRET>> instruction is the recommended way to exit debug mode. However,
-it is a pseudo instruction to return that technically does not execute from the
+it is a pseudoinstruction to return that technically does not execute from the
 program buffer or memory. It currently does not require the <<pcc>> to grant
 <<asr_perm>> so it never excepts.