Hypervisor extension integration (#236)

Integrate CHERI RISC-V with the Hypervisor (H) extension. CHERI is generally
orthogonal to hypervisor, so most of the changes here are limited to
extending the hypervisor-related address CSRs to capability size, adding
enable bits and taking care of XLEN configurations.

---------

Signed-off-by: Andres Amaya Garcia <andres.amaya@codasip.com>
Co-authored-by: Tariq Kurd <tariqandlaura@gmail.com>

src/csv/CHERI_CSR.csv

@@ -22,14 +22,25 @@ Vector range check ^*^ if vectored mode is programmed.","✔","","","","S-mode",
 "sepcc","0x141","sepc","S","SRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
 Always update the CSR with <<SCADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
 direct write if address didn't change","✔","","✔","","S-mode","Supervisor Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
+"vstvecc","0x205","vstvec","VS","HRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
+Always update the CSR with <<SCADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
+Vector range check ^*^ if vectored mode is programmed.","Apply <<section_invalid_addr_conv>>.
+Always update the CSR with <<SCADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
+Vector range check ^*^ if vectored mode is programmed.","✔","","","","H","Virtual Supervisor Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
+"vsscratchc","0x240","vsscratch","VS","HRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<SCADDR>>.","direct write","","","","✔","H","Virtual Supervisor Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
+"vsepcc","0x241","vsepc","VS","HRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
+Always update the CSR with <<SCADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
+direct write if address didn't change","✔","","✔","","H","Virtual Supervisor Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
 "jvtc","0x017","jvt","U","URW","tag=0, otherwise undefined","Apply <<section_invalid_addr_conv>>.
 Always update the CSR with <<SCADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
 direct write if address didn't change","✔","","","","Zcmt","Jump Vector Table Capability","","","","","","","","","","","","","","","","","","","","",""
 "dddc","0x7bc","","D","DRW","tag=0, otherwise undefined","","","","✔","","","{cheri_default_ext_name}, Sdext","Debug Default Data Capability (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","",""
 "mtdc","0x74c","","M","MRW, <<asr_perm>>","tag=0, otherwise undefined","","","","","","","{cheri_default_ext_name}, M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
 "stdc","0x163","","S","SRW, <<asr_perm>>","tag=0, otherwise undefined","","","","","","","{cheri_default_ext_name}, S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
+"vstdc","0x245","","VS","HRW, <<asr_perm>>","tag=0, otherwise undefined","","","","","","","{cheri_default_ext_name}, H","Virtual Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
 "ddc","0x416","","U","URW","<<infinite-cap>>","","","","✔","","","{cheri_default_ext_name}","User Default Data Capability","","","","","","","","","","","","","","","","","","","","",""
 "dinfc","0x7bd","","D","DRW","<<infinite-cap>>","","","","","","✔","Sdext","Source of <<infinite-cap>> capability in debug mode, writes are ignored","","","","","","","","","","","","","","","","","","","","",""
 "utidc","0x480","utid","U","Read: U, Write: U, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<SCADDR>>.","direct write","","","","✔","Zstid","User thread ID","","","","","","","","","","","","","","","","","","","","",""
 "stidc","0x580","stid","S","Read: S, Write: S, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<SCADDR>>.","direct write","","","","✔","Zstid","Supervisor thread ID","","","","","","","","","","","","","","","","","","","","",""
+"vstidc","0xA80","vstid","H","Read: VS, Write: VS, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<SCADDR>>.","direct write","","","","✔","Zstid","Virtual supervisor thread ID","","","","","","","","","","","","","","","","","","","","",""
 "mtidc","0x780","mtid","M","Read: M, Write: M, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<SCADDR>>.","direct write","","","","✔","Zstid","Machine thread ID","","","","","","","","","","","","","","","","","","","","",""