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Fix digital simulation with subcircuits #1167

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Dec 30, 2024
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4 changes: 2 additions & 2 deletions qucs/components/subcircuit.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -244,7 +244,7 @@ QString Subcircuit::vhdlCode(int) {
QString s = " " + Name + ": entity Sub_" + misc::properName(f);

// output all user defined properties
if (Props.at(1) != nullptr) {
if (Props.count() > 1) {
s += " generic map (";
s += Props.at(1)->Value;
for (qsizetype i = 2; i < Props.size(); i++) {
Expand Down Expand Up @@ -274,7 +274,7 @@ QString Subcircuit::verilogCode(int) {
QString s = " Sub_" + misc::properName(f);

// output all user defined properties
if (Props.at(1) != nullptr) {
if (Props.count() > 1) {
s += " #(";
s += misc::Verilog_Param(Props.at(1)->Value);
for (qsizetype i = 2; i < Props.size(); i++)
Expand Down
29 changes: 20 additions & 9 deletions qucs/schematic_file.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1869,7 +1869,8 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QPlainTextEdit *ErrTe



if (QucsSettings.DefaultSimulator == spicecompat::simQucsator) {
if (QucsSettings.DefaultSimulator == spicecompat::simQucsator ||
!a_isAnalog) {

if(a_isAnalog) {
// ..... analog subcircuit ...................................
Expand Down Expand Up @@ -1956,26 +1957,35 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QPlainTextEdit *ErrTe
} else {
// ..... digital subcircuit ...................................
(*tstream) << VHDL_LIBRARIES;
(*tstream) << "entity Sub_" << Type << " is\n"
<< " port ("
<< SubcircuitPortNames.join(";\n ") << ");\n";
(*tstream) << "entity Sub_" << Type << " is\n";

for(pi = a_SymbolPaints.first(); pi != 0; pi = a_SymbolPaints.next())
QString generic_str;
for(pi = a_SymbolPaints.first(); pi != 0; pi = a_SymbolPaints.next()) {
if(pi->Name == ".ID ") {
ID_Text *pid = (ID_Text*)pi;
QList<SubParameter *>::const_iterator it;

(*tstream) << " generic (";


for(it = pid->Parameter.constBegin(); it != pid->Parameter.constEnd(); it++) {
s = (*it)->Name;
QString t = (*it)->Type.isEmpty() ? "real" : (*it)->Type;
(*tstream) << s.replace("=", " : "+t+" := ") << ";\n ";
generic_str += s.replace("=", " : "+t+" := ") + ";\n ";
}

(*tstream) << ");\n";

break;
}
}
if (!generic_str.isEmpty()) {
(*tstream) << " generic (";
(*tstream) << generic_str;
(*tstream) << ");\n";
}

(*tstream) << " port ("
<< SubcircuitPortNames.join(";\n ") << ");\n";


(*tstream) << "end entity;\n"
<< "use work.all;\n"
Expand Down Expand Up @@ -2054,7 +2064,8 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,

// Emit subcircuit components
createSubNetlistPlain(stream, ErrText, NumPorts);
if (QucsSettings.DefaultSimulator != spicecompat::simQucsator) {
if (QucsSettings.DefaultSimulator != spicecompat::simQucsator &&
a_isAnalog) {
AbstractSpiceKernel *kern = new AbstractSpiceKernel(this);
QStringList err_lst;
if (!kern->checkSchematic(err_lst)) {
Expand Down
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