Removed todo in MPU

bhv/cv32e40x_wrapper.sv

@@ -433,6 +433,10 @@ endgenerate
              .write_buffer_txn_bufferable       ('0),
              .write_buffer_txn_cacheable        ('0),
              .obi_if_state                      (core_i.if_stage_i.instruction_obi_i.state_q),
+             .lsu_split_0                       (1'b0),
+             .lsu_split_q                       (1'b0),
+             .lsu_ctrl_update                   (1'b0),
+             .ctrl_exception_wb                 (1'b0),
              .*);
 
   bind cv32e40x_mpu:
@@ -460,6 +464,10 @@ endgenerate
              .write_buffer_txn_bufferable       (core_i.load_store_unit_i.write_buffer_i.trans_o.memtype[0]),
              .write_buffer_txn_cacheable        (core_i.load_store_unit_i.write_buffer_i.trans_o.memtype[1]),
              .obi_if_state                      (cv32e40x_pkg::TRANSPARENT),
+             .lsu_split_0                       (core_i.load_store_unit_i.lsu_split_0_o),
+             .lsu_split_q                       (core_i.load_store_unit_i.split_q),
+             .lsu_ctrl_update                   (core_i.load_store_unit_i.ctrl_update),
+             .ctrl_exception_wb                 (core_i.controller_i.controller_fsm_i.exception_in_wb),
              .*);
 
   bind cv32e40x_lsu_response_filter :

rtl/cv32e40x_mpu.sv

@@ -226,6 +226,4 @@ module cv32e40x_mpu import cv32e40x_pkg::*;
     end
   endgenerate
 
-// TODO:OE any way to check that the 2nd access of a failed misalgn will not reach the MPU?
-
 endmodule

sva/cv32e40x_mpu_sva.sv

@@ -84,7 +84,11 @@ module cv32e40x_mpu_sva import cv32e40x_pkg::*; import uvm_pkg::*;
    input logic        mpu_block_bus,
    input              mpu_state_e state_q,
    input logic        mpu_err,
-   input logic        load_access
+   input logic        load_access,
+   input logic        lsu_split_0,
+   input logic        lsu_split_q,
+   input logic        lsu_ctrl_update,
+   input logic        ctrl_exception_wb
    );
 
   // PMA assertions helper signals
@@ -450,5 +454,21 @@ if (DEBUG) begin
                   !bus_trans_bufferable)
         else `uvm_error("mpu", "Wrong attributes for non-atomic access to DM during debug mode")
 end
+
+generate
+  if (IS_INSTR_SIDE == 0) begin
+    a_misalign_err_block :
+      assert property (@(posedge clk) disable iff (!rst_n)
+                      core_trans_valid_i &&   // MPU gets a valid transaction
+                      lsu_split_0 &&          // LSU is handling first part of split misaligned
+                      mpu_err     &&          // MPU gives an error
+                      lsu_ctrl_update         // LSU passes failed instruction to WB
+                      |=>                     // In the next cycle:
+                      lsu_split_q &&          // LSU is handling second half of split misaligned
+                      !core_trans_valid_i &&  // MPU shall not see a valid input
+                      ctrl_exception_wb)      // and controller shall see an exception
+        else `uvm_error("mpu", "Second part of split misaligned not suppressed on exception from the first")
+  end
+endgenerate
 endmodule : cv32e40x_mpu_sva