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Designed a Single Cycle 6-stage pipelined Processor which can execute 26 different instructions and implemented it in code in VHDL

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Pipelined-Processor-Design

Designed a 6-stage pipelined Processor which can execute 26 different instructions and implemented it in code in VHDL

Course Project - Microprocessors (EE309)

Team Members -

  1. Omkar Nitsure (Roll No - 210070057)
    Github - https://github.com/omkarnitsureiitb
  2. Ojas Karanjkar (Roll No - 210070040)
    Github - https://github.com/Ojas1905
  3. Sanket Kothawade (Roll No - 210070044)
    Github - https://github.com/sankethk1
  4. Kushal Gajbe (Roll No - 210070048)
    Github - https://github.com/KushalGajbe

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Designed a Single Cycle 6-stage pipelined Processor which can execute 26 different instructions and implemented it in code in VHDL

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vhdl pipelined-risc

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