Skip to content
This repository has been archived by the owner on Apr 9, 2024. It is now read-only.

feat(brillig): Allow dynamic-size foreign calls #370

Merged
merged 23 commits into from
Jun 16, 2023
Merged

feat(brillig): Allow dynamic-size foreign calls #370

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
23 commits
Select commit Hold shift + click to select a range
3b1296d
Expand memory on ForeignCall outputs that are greater than the max me…
vezenovm Jun 13, 2023
3793097
Merge
ludamad Jun 13, 2023
0a5fea9
fix: tests
ludamad Jun 13, 2023
f1a040f
Merge again
ludamad Jun 13, 2023
edad613
fix: Spelling
ludamad Jun 13, 2023
081cd7f
fix: Comment
ludamad Jun 13, 2023
feb6d90
fix: Comment
ludamad Jun 13, 2023
2c97e73
fix: Comment
ludamad Jun 13, 2023
dd05610
update vector string concatenation test
vezenovm Jun 14, 2023
83c58dc
switch usage of nested vector to enum ForeignCallOutput
vezenovm Jun 14, 2023
75da5a8
Update brillig_vm/src/opcodes.rs
ludamad Jun 14, 2023
c0c2170
Update brillig_vm/src/opcodes.rs
ludamad Jun 14, 2023
c45862a
Update brillig_vm/src/opcodes.rs
ludamad Jun 14, 2023
0d2d60f
Update lib.rs
ludamad Jun 14, 2023
543dfc2
Update brillig_vm/src/opcodes.rs
ludamad Jun 14, 2023
21f1d2c
Update brillig_vm/src/opcodes.rs
ludamad Jun 14, 2023
7c996c4
Update opcodes.rs
ludamad Jun 14, 2023
0cd2471
Merge branch 'adam/foreign-call-vectors' into mv/foreign-call-res-enum
ludamad Jun 14, 2023
a8db20b
chore(brillig_vm)!: Switch nested vector in ForeignCallResult to enum…
ludamad Jun 14, 2023
dcb94ed
fix: allow size returned from foreign call
ludamad Jun 15, 2023
fa064db
use RegisterOrMemory not ForeignCallInput which does not exist
vezenovm Jun 15, 2023
c3ecc6f
merge conflicts w/ master after switching how we fail on invalid fore…
vezenovm Jun 15, 2023
ee0ef48
cargo fmt
vezenovm Jun 15, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
27 changes: 13 additions & 14 deletions acvm/src/pwg/mod.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -310,7 +310,7 @@ mod tests {
use std::collections::BTreeMap;

use acir::{
brillig_vm::{self, BinaryFieldOp, RegisterIndex, RegisterValueOrArray, Value},
brillig_vm::{self, BinaryFieldOp, RegisterIndex, RegisterOrMemory, Value},
circuit::{
brillig::{Brillig, BrilligInputs, BrilligOutputs},
directives::Directive,
Expand Down Expand Up @@ -483,8 +483,8 @@ mod tests {
// Oracles are named 'foreign calls' in brillig
brillig_vm::Opcode::ForeignCall {
function: "invert".into(),
destinations: vec![RegisterValueOrArray::RegisterIndex(RegisterIndex::from(1))],
inputs: vec![RegisterValueOrArray::RegisterIndex(RegisterIndex::from(0))],
destinations: vec![RegisterOrMemory::RegisterIndex(RegisterIndex::from(1))],
inputs: vec![RegisterOrMemory::RegisterIndex(RegisterIndex::from(0))],
},
],
predicate: None,
Expand Down Expand Up @@ -535,9 +535,8 @@ mod tests {
"Should be waiting for a single input"
);
// As caller of VM, need to resolve foreign calls
let foreign_call_result = vec![Value::from(
foreign_call.foreign_call_wait_info.inputs[0][0].to_field().inverse(),
)];
let foreign_call_result =
Value::from(foreign_call.foreign_call_wait_info.inputs[0][0].to_field().inverse());
// Alter Brillig oracle opcode with foreign call resolution
let brillig: Brillig = foreign_call.resolve(foreign_call_result.into());
let mut next_opcodes_for_solving = vec![Opcode::Brillig(brillig)];
Expand Down Expand Up @@ -611,13 +610,13 @@ mod tests {
// Oracles are named 'foreign calls' in brillig
brillig_vm::Opcode::ForeignCall {
function: "invert".into(),
destinations: vec![RegisterValueOrArray::RegisterIndex(RegisterIndex::from(1))],
inputs: vec![RegisterValueOrArray::RegisterIndex(RegisterIndex::from(0))],
destinations: vec![RegisterOrMemory::RegisterIndex(RegisterIndex::from(1))],
inputs: vec![RegisterOrMemory::RegisterIndex(RegisterIndex::from(0))],
},
brillig_vm::Opcode::ForeignCall {
function: "invert".into(),
destinations: vec![RegisterValueOrArray::RegisterIndex(RegisterIndex::from(3))],
inputs: vec![RegisterValueOrArray::RegisterIndex(RegisterIndex::from(2))],
destinations: vec![RegisterOrMemory::RegisterIndex(RegisterIndex::from(3))],
inputs: vec![RegisterOrMemory::RegisterIndex(RegisterIndex::from(2))],
},
],
predicate: None,
Expand Down Expand Up @@ -673,7 +672,7 @@ mod tests {
let x_plus_y_inverse =
foreign_call.foreign_call_wait_info.inputs[0][0].to_field().inverse();
// Alter Brillig oracle opcode
let brillig: Brillig = foreign_call.resolve(vec![Value::from(x_plus_y_inverse)].into());
let brillig: Brillig = foreign_call.resolve(Value::from(x_plus_y_inverse).into());

let mut next_opcodes_for_solving = vec![Opcode::Brillig(brillig)];
next_opcodes_for_solving.extend_from_slice(&unsolved_opcodes[..]);
Expand All @@ -699,7 +698,7 @@ mod tests {
foreign_call.foreign_call_wait_info.inputs[0][0].to_field().inverse();
assert_ne!(x_plus_y_inverse, i_plus_j_inverse);
// Alter Brillig oracle opcode
let brillig = foreign_call.resolve(vec![Value::from(i_plus_j_inverse)].into());
let brillig = foreign_call.resolve(Value::from(i_plus_j_inverse).into());

let mut next_opcodes_for_solving = vec![Opcode::Brillig(brillig)];
next_opcodes_for_solving.extend_from_slice(&unsolved_opcodes[..]);
Expand Down Expand Up @@ -759,8 +758,8 @@ mod tests {
// Oracles are named 'foreign calls' in brillig
brillig_vm::Opcode::ForeignCall {
function: "invert".into(),
destinations: vec![RegisterValueOrArray::RegisterIndex(RegisterIndex::from(1))],
inputs: vec![RegisterValueOrArray::RegisterIndex(RegisterIndex::from(0))],
destinations: vec![RegisterOrMemory::RegisterIndex(RegisterIndex::from(1))],
inputs: vec![RegisterOrMemory::RegisterIndex(RegisterIndex::from(0))],
},
],
predicate: Some(Expression::default()),
Expand Down
Loading