enigmaFPGA

Enigma in FPGA, made for learning Verilog as part of presentation on BalcCon 2017.

Version of code from conference is at separate branch (Balccon2017): https://github.com/mmicko/enigmafpga/tree/Balccon2017

Due to limitation of presentation uart_rx and uart_tx modules are used from : https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html

Project contains build files for various targets.

More explanation and Javascript reference application at : http://enigma.louisedade.co.uk/enigma.html

Name		Name	Last commit message	Last commit date
Latest commit History 17 Commits
.gitignore		.gitignore
FPGA U-Boat.pdf		FPGA U-Boat.pdf
FPGA U-Boat.pptx		FPGA U-Boat.pptx
Go_Board_Constraints.pcf		Go_Board_Constraints.pcf
LICENSE		LICENSE
Makefile		Makefile
README.md		README.md
blackice.pcf		blackice.pcf
cdd_2_lcov.py		cdd_2_lcov.py
checkKnockpoints.v		checkKnockpoints.v
decodeASCII.v		decodeASCII.v
encode.v		encode.v
encodeASCII.v		encodeASCII.v
enigma.vlt		enigma.vlt
enigmaFPGA.core		enigmaFPGA.core
enigma_top.v		enigma_top.v
enigma_top_bi.v		enigma_top_bi.v
gen_rotors_mem.sh		gen_rotors_mem.sh
generate.py		generate.py
hex_to_7seg.v		hex_to_7seg.v
main.cpp		main.cpp
plugboardEncode.v		plugboardEncode.v
reflectorEncode.v		reflectorEncode.v
rotor.v		rotor.v
rotorEncode.v		rotorEncode.v
state_machine.v		state_machine.v
test.v		test.v
testrotor.v		testrotor.v
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v
verilated_cov_2_lcov.py		verilated_cov_2_lcov.py

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