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espressif: extend loader data
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Add additional regions in loader to include
RTC, LP, IROM and DROM information.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
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sylvioalves committed Jan 13, 2025
1 parent 59e9f03 commit 2caa9d6
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Showing 2 changed files with 53 additions and 8 deletions.
29 changes: 21 additions & 8 deletions boot/espressif/hal/include/esp_mcuboot_image.h
Original file line number Diff line number Diff line change
Expand Up @@ -15,12 +15,25 @@
* for MCUboot-Espressif port booting.
*/
typedef struct esp_image_load_header {
uint32_t header_magic; /* Magic for load header */
uint32_t entry_addr; /* Application entry address */
uint32_t iram_dest_addr; /* Destination address(VMA) for IRAM region */
uint32_t iram_flash_offset; /* Flash offset(LMA) for start of IRAM region */
uint32_t iram_size; /* Size of IRAM region */
uint32_t dram_dest_addr; /* Destination address(VMA) for DRAM region */
uint32_t dram_flash_offset; /* Flash offset(LMA) for start of DRAM region */
uint32_t dram_size; /* Size of DRAM region */
uint32_t header_magic; /* Magic for load header */
uint32_t entry_addr; /* Application entry address */
uint32_t iram_dest_addr; /* Destination address(VMA) for IRAM region */
uint32_t iram_flash_offset; /* Flash offset(LMA) for start of IRAM region */
uint32_t iram_size; /* Size of IRAM region */
uint32_t dram_dest_addr; /* Destination address(VMA) for DRAM region */
uint32_t dram_flash_offset; /* Flash offset(LMA) for start of DRAM region */
uint32_t dram_size; /* Size of DRAM region */
uint32_t lp_rtc_iram_dest_addr; /* Destination address (VMA) for LP_IRAM region */
uint32_t lp_rtc_iram_flash_offset; /* Flash offset (LMA) for LP_IRAM region */
uint32_t lp_rtc_iram_size; /* Size of LP_IRAM region */
uint32_t lp_rtc_dram_dest_addr; /* Destination address (VMA) for LP_DRAM region */
uint32_t lp_rtc_dram_flash_offset; /* Flash offset (LMA) for LP_DRAM region */
uint32_t lp_rtc_dram_size; /* Size of LP_DRAM region */
uint32_t irom_map_addr; /* Mapped address (VMA) for IROM region */
uint32_t irom_flash_offset; /* Flash offset (LMA) for IROM region */
uint32_t irom_size; /* Size of IROM region */
uint32_t drom_map_addr; /* Mapped address (VMA) for DROM region */
uint32_t drom_flash_offset; /* Flash offset (LMA) for DROM region */
uint32_t drom_size; /* Size of DROM region */
uint32_t _reserved[4]; /* Up to 24 words reserved for the header */
} esp_image_load_header_t;
32 changes: 32 additions & 0 deletions boot/espressif/port/esp_loader.c
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,11 @@
#include "app_cpu_start.h"
#endif

#include "esp_rom_sys.h"
#include "esp_cpu.h"

#define LP_RTC_PREFIX "LP"

static int load_segment(const struct flash_area *fap, uint32_t data_addr, uint32_t data_len, uint32_t load_addr)
{
const uint32_t *data = (const uint32_t *)bootloader_mmap((fap->fa_off + data_addr), data_len);
Expand Down Expand Up @@ -80,6 +85,33 @@ void esp_app_image_load(int image_index, int slot, unsigned int hdr_offset, unsi
BOOT_LOG_INF("IRAM segment: start=0x%x, size=0x%x, vaddr=0x%x", fap->fa_off + load_header.iram_flash_offset, load_header.iram_size, load_header.iram_dest_addr);
load_segment(fap, load_header.iram_flash_offset, load_header.iram_size, load_header.iram_dest_addr);

#if SOC_RTC_FAST_MEM_SUPPORTED || SOC_RTC_SLOW_MEM_SUPPORTED
if (load_header.lp_rtc_dram_size > 0) {
soc_reset_reason_t reset_reason = esp_rom_get_reset_reason(0);

/* Unless waking from deep sleep (implying RTC memory is intact), load its segments */
if (reset_reason != RESET_REASON_CORE_DEEP_SLEEP) {
BOOT_LOG_INF("%s_RAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load", LP_RTC_PREFIX,
(fap->fa_off + load_header.lp_rtc_dram_flash_offset), load_header.lp_rtc_dram_dest_addr,
load_header.lp_rtc_dram_size, load_header.lp_rtc_dram_size);
load_segment(fap, load_header.lp_rtc_dram_flash_offset,
load_header.lp_rtc_dram_size, load_header.lp_rtc_dram_dest_addr);
} else {
BOOT_LOG_INF("%s_RAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) noload", LP_RTC_PREFIX,
load_header.lp_rtc_dram_flash_offset, load_header.lp_rtc_dram_dest_addr,
load_header.lp_rtc_dram_size, load_header.lp_rtc_dram_size);
}
}

if (load_header.lp_rtc_iram_size > 0) {
BOOT_LOG_INF("%s_IRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load", LP_RTC_PREFIX,
(fap->fa_off + load_header.lp_rtc_iram_flash_offset), load_header.lp_rtc_iram_dest_addr,
load_header.lp_rtc_iram_size, load_header.lp_rtc_iram_size);
load_segment(fap, load_header.lp_rtc_iram_flash_offset,
load_header.lp_rtc_iram_size, load_header.lp_rtc_iram_dest_addr);
}
#endif

BOOT_LOG_INF("start=0x%x", load_header.entry_addr);
uart_tx_wait_idle(0);

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