NuttX for SG2000

.gitignore

@@ -65,3 +65,8 @@ tools/gdb/__pycache__
 /build
 .ccls-cache
 compile_commands.json
+Image
+initrd
+root-riscv64.cfg
+hello.S
+init.S

arch/risc-v/src/bl808/Make.defs

@@ -27,4 +27,4 @@ HEAD_ASRC = bl808_head.S
 # Specify our C code within this directory to be included
 CHIP_CSRCS  = bl808_start.c bl808_irq_dispatch.c bl808_irq.c
 CHIP_CSRCS += bl808_timerisr.c bl808_allocateheap.c
-CHIP_CSRCS += bl808_mm_init.c bl808_pgalloc.c bl808_serial.c
+CHIP_CSRCS += bl808_mm_init.c bl808_pgalloc.c

arch/risc-v/src/bl808/bl808_head.S

@@ -69,6 +69,25 @@ __start:
 
 real_start:
 
+  /* Print `123` to UART */
+  /* Load UART Base Address to Register t0 */
+  li  t0, 0x04140000
+
+  /* Load `1` to Register t1 */
+  li  t1, 0x31
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
+  /* Load `2` to Register t1 */
+  li  t1, 0x32
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
+  /* Load `3` to Register t1 */
+  li  t1, 0x33
+  /* Store byte from Register t1 to UART Base Address, Offset 0 */
+  sb  t1, 0(t0)
+
   /* Load the number of CPUs that the kernel supports */
 
 #ifdef CONFIG_SMP

arch/risc-v/src/bl808/bl808_mm_init.c

@@ -52,7 +52,7 @@
 #define MMU_IO_BASE      (0x00000000ul)
 #define MMU_IO_SIZE      (0x40000000ul)
 
-#define MMU_INT_BASE     (0xe0000000ul)
+#define MMU_INT_BASE     (0x70000000ul)
 #define MMU_INT_SIZE     (0x10000000ul)
 
 /* Physical and virtual addresses to page tables (vaddr = paddr mapping) */

arch/risc-v/src/bl808/bl808_start.c

@@ -314,7 +314,7 @@ void bl808_start(int mhartid)
 
 void riscv_earlyserialinit(void)
 {
-  bl808_earlyserialinit();
+  u16550_earlyserialinit();
 }
 
 /****************************************************************************
@@ -328,5 +328,5 @@ void riscv_earlyserialinit(void)
 
 void riscv_serialinit(void)
 {
-  bl808_serialinit();
+  u16550_serialinit();
 }

arch/risc-v/src/bl808/hardware/bl808_memorymap.h

@@ -27,7 +27,7 @@
 
 /* Register Base Address ****************************************************/
 
-#define BL808_UART3_BASE   0x30002000ul
-#define BL808_PLIC_BASE    0xe0000000ul
+//// TODO: #define BL808_UART3_BASE   0x30002000ul
+#define BL808_PLIC_BASE    0x70000000ul
 
 #endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MEMORYMAP_H */

boards/risc-v/bl808/ox64/configs/nsh/defconfig

@@ -7,39 +7,53 @@
 #
 # CONFIG_DISABLE_OS_API is not set
 # CONFIG_NSH_DISABLE_LOSMART is not set
-# CONFIG_STANDARD_SERIAL is not set
+CONFIG_16550_ADDRWIDTH=0
+CONFIG_16550_REGINCR=4
+CONFIG_16550_UART0=y
+CONFIG_16550_UART0_BASE=0x04140000
+CONFIG_16550_UART0_CLOCK=23040000
+CONFIG_16550_UART0_IRQ=69
+CONFIG_16550_UART0_SERIAL_CONSOLE=y
+CONFIG_16550_UART=y
+CONFIG_16550_WAIT_LCR=y
 CONFIG_ARCH="risc-v"
 CONFIG_ARCH_ADDRENV=y
 CONFIG_ARCH_BOARD="ox64"
 CONFIG_ARCH_BOARD_BL808_OX64=y
 CONFIG_ARCH_CHIP="bl808"
 CONFIG_ARCH_CHIP_BL808=y
 CONFIG_ARCH_DATA_NPAGES=128
-CONFIG_ARCH_DATA_VBASE=0x80100000
+CONFIG_ARCH_DATA_VBASE=0xC0100000
 CONFIG_ARCH_HEAP_NPAGES=128
-CONFIG_ARCH_HEAP_VBASE=0x80200000
+CONFIG_ARCH_HEAP_VBASE=0xC0200000
 CONFIG_ARCH_INTERRUPTSTACK=2048
 CONFIG_ARCH_KERNEL_STACKSIZE=3072
 CONFIG_ARCH_PGPOOL_MAPPING=y
-CONFIG_ARCH_PGPOOL_PBASE=0x50600000
+CONFIG_ARCH_PGPOOL_PBASE=0x80600000
 CONFIG_ARCH_PGPOOL_SIZE=4194304
-CONFIG_ARCH_PGPOOL_VBASE=0x50600000
+CONFIG_ARCH_PGPOOL_VBASE=0x80600000
 CONFIG_ARCH_RISCV=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH_TEXT_NPAGES=128
-CONFIG_ARCH_TEXT_VBASE=0x80000000
+CONFIG_ARCH_TEXT_VBASE=0xC0000000
 CONFIG_ARCH_USE_MMU=y
 CONFIG_ARCH_USE_MPU=y
 CONFIG_ARCH_USE_S_MODE=y
-CONFIG_BL808_UART3=y
 CONFIG_BOARDCTL_ROMDISK=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=1120
 CONFIG_BUILD_KERNEL=y
 CONFIG_DEBUG_ASSERTIONS=y
 CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y
+CONFIG_DEBUG_BINFMT=y
+CONFIG_DEBUG_BINFMT_ERROR=y
+CONFIG_DEBUG_BINFMT_WARN=y
 CONFIG_DEBUG_FEATURES=y
 CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SCHED=y
+CONFIG_DEBUG_SCHED_ERROR=y
+CONFIG_DEBUG_SCHED_INFO=y
+CONFIG_DEBUG_SCHED_WARN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_ZERO=y
 CONFIG_ELF=y
@@ -67,11 +81,12 @@ CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_READLINE=y
 CONFIG_PATH_INITIAL="/system/bin"
 CONFIG_RAM_SIZE=1048576
-CONFIG_RAM_START=0x50200000
+CONFIG_RAM_START=0x80200000
 CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_WAITPID=y
+CONFIG_SERIAL_UART_ARCH_MMIO=y
 CONFIG_STACK_COLORATION=y
 CONFIG_START_MONTH=12
 CONFIG_START_YEAR=2021
@@ -80,6 +95,4 @@ CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_PROGNAME="init"
 CONFIG_TESTING_GETPRIME=y
 CONFIG_TESTING_OSTEST=y
-CONFIG_UART3_BAUD=2000000
-CONFIG_UART3_SERIAL_CONSOLE=y
 CONFIG_USEC_PER_TICK=1000

boards/risc-v/bl808/ox64/scripts/ld.script

@@ -20,10 +20,10 @@
 
 MEMORY
 {
-    kflash (rx) : ORIGIN = 0x50200000, LENGTH = 2048K   /* w/ cache */
-    ksram (rwx) : ORIGIN = 0x50400000, LENGTH = 2048K   /* w/ cache */
-    pgram (rwx) : ORIGIN = 0x50600000, LENGTH = 4096K   /* w/ cache */
-    ramdisk (rwx) : ORIGIN = 0x50A00000, LENGTH = 16M   /* w/ cache */
+    kflash (rx) : ORIGIN = 0x80200000, LENGTH = 2048K   /* w/ cache */
+    ksram (rwx) : ORIGIN = 0x80400000, LENGTH = 2048K   /* w/ cache */
+    pgram (rwx) : ORIGIN = 0x80600000, LENGTH = 4096K   /* w/ cache */
+    ramdisk (rwx) : ORIGIN = 0x80A00000, LENGTH = 16M   /* w/ cache */
 }
 
 OUTPUT_ARCH("riscv")
@@ -49,7 +49,7 @@ __ramdisk_end  = ORIGIN(ramdisk) + LENGTH(ramdisk);
 
 SECTIONS
 {
-  . = 0x50200000;
+  . = 0x80200000;
 
   .text :
     {

drivers/serial/uart_16550.c

@@ -818,11 +818,13 @@ static int u16550_setup(FAR struct uart_dev_s *dev)
 
   u16550_serialout(priv, UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
 
+#ifdef TODO ////
   /* Set the BAUD divisor */
 
   div = u16550_divisor(priv);
   u16550_serialout(priv, UART_DLM_OFFSET, div >> 8);
   u16550_serialout(priv, UART_DLL_OFFSET, div & 0xff);
+#endif //// TODO
 
 #ifdef CONFIG_16550_WAIT_LCR
   /* Wait till UART is not busy before setting LCR */