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[WIP] [CodeGen] Enable TrapUnreachable by default for all targets. #109732

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[WIP] [CodeGen] Enable TrapUnreachable by default for all targets. #109732

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2 changes: 1 addition & 1 deletion llvm/include/llvm/Target/TargetOptions.h
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Expand Up @@ -145,7 +145,7 @@ namespace llvm {
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
UniqueBasicBlockSectionNames(false), SeparateNamedSections(false),
TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
TrapUnreachable(true), NoTrapAfterNoreturn(true), TLSSize(0),
EmulatedTLS(false), EnableTLSDESC(false), EnableIPRA(false),
EmitStackSizeSection(false), EnableMachineOutliner(false),
EnableMachineFunctionSplitter(false), SupportsDefaultOutlining(false),
Expand Down
21 changes: 13 additions & 8 deletions llvm/lib/CodeGen/LLVMTargetMachine.cpp
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Expand Up @@ -33,11 +33,11 @@
#include "llvm/Target/TargetOptions.h"
using namespace llvm;

static cl::opt<bool>
EnableTrapUnreachable("trap-unreachable", cl::Hidden,
cl::desc("Enable generating trap for unreachable"));
cl::opt<bool> EnableTrapUnreachable(
"trap-unreachable", cl::Hidden,
cl::desc("Enable generating trap for unreachable"));

static cl::opt<bool> EnableNoTrapAfterNoreturn(
cl::opt<bool> EnableNoTrapAfterNoreturn(
"no-trap-after-noreturn", cl::Hidden,
cl::desc("Do not emit a trap instruction for 'unreachable' IR instructions "
"after noreturn calls, even if --trap-unreachable is set."));
Expand Down Expand Up @@ -96,10 +96,15 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T,
this->CMModel = CM;
this->OptLevel = OL;

if (EnableTrapUnreachable)
this->Options.TrapUnreachable = true;
if (EnableNoTrapAfterNoreturn)
this->Options.NoTrapAfterNoreturn = true;
if (EnableTrapUnreachable.getNumOccurrences())
this->Options.TrapUnreachable = EnableTrapUnreachable;

if (EnableNoTrapAfterNoreturn.getNumOccurrences())
this->Options.NoTrapAfterNoreturn = EnableNoTrapAfterNoreturn;

// Keep all traps in debug environments.
else if (OL == CodeGenOptLevel::None)
this->Options.NoTrapAfterNoreturn = false;
}

TargetTransformInfo
Expand Down
6 changes: 1 addition & 5 deletions llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
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Expand Up @@ -360,11 +360,6 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
initAsmInfo();

if (TT.isOSBinFormatMachO()) {
this->Options.TrapUnreachable = true;
this->Options.NoTrapAfterNoreturn = true;
}

if (getMCAsmInfo()->usesWindowsCFI()) {
// Unwinding can get confused if the last instruction in an
// exception-handling region (function, funclet, try block, etc.)
Expand All @@ -373,6 +368,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
// FIXME: We could elide the trap if the next instruction would be in
// the same region anyway.
this->Options.TrapUnreachable = true;
this->Options.NoTrapAfterNoreturn = false;
}

if (this->Options.TLSSize == 0) // default
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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Expand Up @@ -396,6 +396,8 @@ static cl::opt<bool>
cl::desc("Enable AMDGPUAttributorPass"),
cl::init(true), cl::Hidden);

extern cl::opt<bool> EnableTrapUnreachable;

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
// Register the target
RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
Expand Down Expand Up @@ -612,6 +614,10 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
TLOF(createTLOF(getTargetTriple())) {
// FIXME: There are some scenarios where targets may not have hardware traps,
// and external calls to `abort` also fail. For now, do a blanket-disable.
if (!EnableTrapUnreachable.getNumOccurrences())
this->Options.TrapUnreachable = false;
Comment on lines 616 to +620
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Targets should not have to flip bits in this setting like this

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@duk-37 duk-37 Sep 24, 2024 •
edited
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This is already happening all over the place though. See PS4/PS5 in X86, WASM, AArch64, etc. That being said, it definitely isn't great.

initAsmInfo();
if (TT.getArch() == Triple::amdgcn) {
if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
Expand Down
5 changes: 0 additions & 5 deletions llvm/lib/Target/ARM/ARMTargetMachine.cpp
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Expand Up @@ -251,11 +251,6 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
this->Options.EABIVersion = EABI::EABI5;
}

if (TT.isOSBinFormatMachO()) {
this->Options.TrapUnreachable = true;
this->Options.NoTrapAfterNoreturn = true;
}

// ARM supports the debug entry values.
setSupportsDebugEntryValues(true);

Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/BPF/BPFTargetMachine.cpp
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Expand Up @@ -34,6 +34,8 @@
#include <optional>
using namespace llvm;

extern cl::opt<bool> EnableTrapUnreachable;

static cl::
opt<bool> DisableMIPeephole("disable-bpf-peephole", cl::Hidden,
cl::desc("Disable machine peepholes for BPF"));
Expand Down Expand Up @@ -74,6 +76,12 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
// FIXME: If the user has not explicitly enabled TrapUnreachable,
// disable it. We do not have an explicit trap opcode and external calls
// to abort are a no-no.
if (!EnableTrapUnreachable.getNumOccurrences())
this->Options.TrapUnreachable = false;

initAsmInfo();

BPFMCAsmInfo *MAI =
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
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Expand Up @@ -146,6 +146,8 @@ static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
cl::init(true),
cl::desc("Enable instsimplify"));

extern cl::opt<bool> EnableTrapUnreachable;

/// HexagonTargetMachineModule - Note that this is used on hosts that
/// cannot link in a library unless there are references into the
/// library. In particular, it seems that it is not possible to get
Expand Down Expand Up @@ -284,6 +286,11 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
(HexagonNoOpt ? CodeGenOptLevel::None : OL)),
TLOF(std::make_unique<HexagonTargetObjectFile>()),
Subtarget(Triple(TT), CPU, FS, *this) {
// FIXME: If the user has not explicitly enabled TrapUnreachable,
// disable it. We currently seem to have problems with EH_RETURN lowering.
if (!EnableTrapUnreachable.getNumOccurrences())
this->Options.TrapUnreachable = false;

initializeHexagonCopyHoistingPass(*PassRegistry::getPassRegistry());
initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
initializeHexagonLoopAlignPass(*PassRegistry::getPassRegistry());
Expand Down
7 changes: 4 additions & 3 deletions llvm/lib/Target/X86/X86TargetMachine.cpp
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Expand Up @@ -242,10 +242,11 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
OL),
TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
// On PS4/PS5, the "return address" of a 'noreturn' call must still be within
// the calling function, and TrapUnreachable is an easy way to get that.
if (TT.isPS() || TT.isOSBinFormatMachO()) {
// the calling function, and unsetting NoTrapAfterNoreturn
// is an easy way to get that.
if (TT.isPS()) {
this->Options.TrapUnreachable = true;
this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
this->Options.NoTrapAfterNoreturn = false;
}

setMachineOutliner(true);
Expand Down
16 changes: 16 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
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Expand Up @@ -137,6 +137,8 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
; CHECK-NEXT: bb.2.odd:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.next:
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
Expand Down Expand Up @@ -1147,18 +1149,28 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.sw.bb2.i41:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.sw.bb7.i44:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.sw.bb8.i45:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.sw.bb13.i47:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.sw.bb14.i48:
; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C5]]
; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.10
Expand Down Expand Up @@ -1202,6 +1214,8 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: bb.8.sw.default.i49:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.9.sw.bb1.i:
; CHECK-NEXT: G_BR %bb.16
; CHECK-NEXT: {{ $}}
Expand Down Expand Up @@ -1234,6 +1248,7 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @jt_2_tables_phi_edge_from_second, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.18.while.end:
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C21]](s32), %bb.30, [[PHI]](s32), %bb.16
Expand Down Expand Up @@ -1460,6 +1475,7 @@ define i1 @i1_value_cmp_is_signed(i1) {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.OkValue:
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC1]](s1)
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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Expand Up @@ -431,8 +431,7 @@ end:

; CHECK-LABEL: name: unreachable
; CHECK: G_ADD
; CHECK-NEXT: {{^$}}
; CHECK-NEXT: ...
; CHECK-NEXT: G_TRAP
define void @unreachable(i32 %a) {
%sum = add i32 %a, %a
unreachable
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/arm64-big-endian-eh.ll
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Expand Up @@ -71,6 +71,6 @@ declare void @_ZSt9terminatev()
; CHECK-LABEL: Contents of section .eh_frame:
; CHECK-NEXT: {{^ 0000}}
; CHECK-NEXT: {{^ 0010}}
; CHECK-NEXT: 0020 0000000c 00440e10 9e040000 0000001c .....D..........
; CHECK-NEXT: 0020 00000010 00440e10 9e040000 0000001c .....D..........
; CHECK-NEXT: 0030 00000000 017a504c 5200017c 1e0b9c00 .....zPLR..|....

1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/ptrauth-invoke.ll
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Expand Up @@ -173,6 +173,7 @@ continuebb:
; ELF-NEXT: blrab x19, x17
; ELF-NEXT: [[POSTCALL:.L.*]]:
; ELF-NEXT: // %bb.1:
; ELF-NEXT: brk #0x1
; ELF-NEXT: [[LPADBB:.LBB[0-9_]+]]:
; ELF-NEXT: [[LPAD:.L.*]]:
; ELF-NEXT: mov x19, x1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
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Expand Up @@ -22,7 +22,7 @@ entry:
; for.body -> for.cond.backedge (100%)
; -> cond.false.i (0%)
; CHECK: bb.1.for.body:
; CHECK: successors: %bb.2(0x80000000), %bb.5(0x00000000)
; CHECK: successors: %bb.2(0x80000000), %bb.4(0x00000000)
for.body:
br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1

Expand Down
3 changes: 2 additions & 1 deletion llvm/test/CodeGen/ARM/machine-sink-multidef.ll
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Expand Up @@ -23,7 +23,8 @@ define arm_aapcscc void @g() {
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: ldr r1, [r1, #4]
; CHECK-NEXT: bl k
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .inst 0xe7ffdefe
; CHECK-NEXT: .p2align 2 @ trap
; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long f
Expand Down
10 changes: 8 additions & 2 deletions llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
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Expand Up @@ -270,8 +270,11 @@ define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
; CHECK-NEXT: @ %bb.1: @ %if.else
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: bl exit
; CHECK-NEXT: .LBB11_2: @ %if.then
; CHECK-NEXT: .inst 0xe7ffdefe
; CHECK-NEXT: .LBB11_2: @ trap
; CHECK-NEXT: @ %if.then
; CHECK-NEXT: bl abort
; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
Expand Down Expand Up @@ -302,9 +305,12 @@ define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
; CHECK-NEXT: bhs .LBB12_2
; CHECK-NEXT: @ %bb.1: @ %if.then
; CHECK-NEXT: bl abort
; CHECK-NEXT: .LBB12_2: @ %if.else
; CHECK-NEXT: .inst 0xe7ffdefe
; CHECK-NEXT: .LBB12_2: @ trap
; CHECK-NEXT: @ %if.else
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: bl exit
; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/trap-unreachable.ll
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@@ -1,4 +1,4 @@
; RUN: llc -mtriple=thumbv7 -trap-unreachable < %s | FileCheck %s --check-prefixes CHECK,TRAP_UNREACHABLE
; RUN: llc -mtriple=thumbv7 -trap-unreachable -no-trap-after-noreturn=false < %s | FileCheck %s --check-prefixes CHECK,TRAP_UNREACHABLE
; RUN: llc -mtriple=thumbv7 -trap-unreachable -no-trap-after-noreturn < %s | FileCheck %s --check-prefixes CHECK,NTANR

define void @test_trap_unreachable() #0 {
Expand Down
13 changes: 6 additions & 7 deletions llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
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Expand Up @@ -18,9 +18,9 @@ define void @main() {
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: beq .LBB0_7
; CHECK-NEXT: beq .LBB0_6
; CHECK-NEXT: @ %bb.1: @ %for.cond7.preheader.i.lr.ph.i.i
; CHECK-NEXT: bne .LBB0_7
; CHECK-NEXT: bne .LBB0_6
; CHECK-NEXT: .LBB0_2: @ %for.cond14.preheader.us.i.i.i
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cbnz r0, .LBB0_6
Expand All @@ -35,8 +35,8 @@ define void @main() {
; CHECK-NEXT: .LJTI0_0:
; CHECK-NEXT: b.w .LBB0_5
; CHECK-NEXT: b.w .LBB0_6
; CHECK-NEXT: b.w .LBB0_8
; CHECK-NEXT: b.w .LBB0_7
; CHECK-NEXT: b.w .LBB0_6
; CHECK-NEXT: b.w .LBB0_6
; CHECK-NEXT: b.w .LBB0_6
; CHECK-NEXT: b.w .LBB0_6
; CHECK-NEXT: b.w .LBB0_6
Expand All @@ -48,9 +48,8 @@ define void @main() {
; CHECK-NEXT: .LBB0_5: @ %for.cond14.preheader.us.i.i.i
; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .LBB0_6: @ %func_1.exit.loopexit
; CHECK-NEXT: .LBB0_7: @ %for.end476.i.i.i.loopexit
; CHECK-NEXT: .LBB0_8: @ %lbl_1394.i.i.i.loopexit
; CHECK-NEXT: .LBB0_6: @ %lbl_1394.i.i.i.loopexit
; CHECK-NEXT: .inst.n 0xdefe
entry:
%0 = load volatile ptr, ptr @g_566, align 4
br label %func_16.exit.i.i.i
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/ARM/vcge.ll
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Expand Up @@ -289,6 +289,7 @@ define void @test_vclez_fp(ptr %A) nounwind optsize {
; CHECK-NEXT: vuzp.8 d16, d18
; CHECK-NEXT: vadd.i8 d16, d16, d17
; CHECK-NEXT: vst1.8 {d16}, [r0]
; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%ld = load <4 x float>, ptr %A
%0 = fcmp ole <4 x float> %ld, zeroinitializer
Expand Down
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/ARM/vector-DAGCombine.ll
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Expand Up @@ -27,6 +27,7 @@ bb.i19: ; preds = %bb.i19, %bb3
define void @test_illegal_build_vector() nounwind {
; CHECK-LABEL: test_illegal_build_vector:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .inst 0xe7ffdefe
entry:
store <2 x i64> undef, ptr undef, align 16
%0 = load <16 x i8>, ptr undef, align 16 ; <<16 x i8>> [#uses=1]
Expand All @@ -40,6 +41,7 @@ entry:
define void @test_pr22678() {
; CHECK-LABEL: test_pr22678:
; CHECK: @ %bb.0:
; CHECK-NEXT: .inst 0xe7ffdefe
%1 = fptoui <16 x float> undef to <16 x i8>
store <16 x i8> %1, ptr undef
ret void
Expand Down
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/ARM/vmov.ll
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Expand Up @@ -678,6 +678,7 @@ define arm_aapcs_vfpcc void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp
; CHECK-LE-NEXT: vsub.i32 q8, q8, q1
; CHECK-LE-NEXT: vmovn.i32 d16, q8
; CHECK-LE-NEXT: vst1.16 {d16}, [r0]
; CHECK-LE-NEXT: .inst 0xe7ffdefe
;
; CHECK-BE-LABEL: any_extend:
; CHECK-BE: @ %bb.0: @ %entry
Expand All @@ -689,6 +690,7 @@ define arm_aapcs_vfpcc void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp
; CHECK-BE-NEXT: vsub.i32 q8, q8, q9
; CHECK-BE-NEXT: vmovn.i32 d16, q8
; CHECK-BE-NEXT: vst1.16 {d16}, [r0]
; CHECK-BE-NEXT: .inst 0xe7ffdefe
entry:
%and.i186 = zext <4 x i1> %x to <4 x i32>
%add.i185 = sub <4 x i32> %and.i186, %y
Expand Down
3 changes: 3 additions & 0 deletions llvm/test/CodeGen/ARM/vmul.ll
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Expand Up @@ -728,6 +728,7 @@ define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
define void @vmull_buildvector() nounwind optsize ssp align 2 {
; CHECK-LABEL: vmull_buildvector:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .inst 0xe7ffdefe
entry:
br i1 undef, label %for.end179, label %for.body.lr.ph

Expand Down Expand Up @@ -804,6 +805,7 @@ declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
define void @no_illegal_types_vmull_sext(<4 x i32> %a) {
; CHECK-LABEL: no_illegal_types_vmull_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%wide.load283.i = load <4 x i8>, ptr undef, align 1
%0 = sext <4 x i8> %wide.load283.i to <4 x i32>
Expand All @@ -816,6 +818,7 @@ entry:
define void @no_illegal_types_vmull_zext(<4 x i32> %a) {
; CHECK-LABEL: no_illegal_types_vmull_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%wide.load283.i = load <4 x i8>, ptr undef, align 1
%0 = zext <4 x i8> %wide.load283.i to <4 x i32>
Expand Down
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