[RISCV] Remove riscv-experimental-rv64-legal-i32. #102509
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This has received no development work in a while and is slowly bit rotting as new extensions are added. At the moment, I don't think this is viable without adding a new invariant that 32 bit values are always in sign extended form like Mips64 does. We are very dependent on computeKnownBits and ComputeNumSignBits in SelectionDAG to remove sign extends created for ABI reasons. If we can't propagate sign bit information, we can't clean those up effectively.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThis has received no development work in a while and is slowly bit rotting as new extensions are added. At the moment, I don't think this is viable without adding a new invariant that 32 bit values are always in sign extended form like Mips64 does. We are very dependent on computeKnownBits and ComputeNumSignBits in SelectionDAG to remove sign extends created for ABI reasons. If we can't propagate sign bit information through 64-bit values in SelectionDAG, we can't effectively clean up those extends. Patch is 618.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/102509.diff 31 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b7a1a27a0f69c7..a9f6f1a463796d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -76,10 +76,6 @@ static cl::opt<int>
"use for creating a floating-point immediate value"),
cl::init(2));
-static cl::opt<bool>
- RV64LegalI32("riscv-experimental-rv64-legal-i32", cl::ReallyHidden,
- cl::desc("Make i32 a legal type for SelectionDAG on RV64."));
-
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
: TargetLowering(TM), Subtarget(STI) {
@@ -119,8 +115,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// Set up the register classes.
addRegisterClass(XLenVT, &RISCV::GPRRegClass);
- if (Subtarget.is64Bit() && RV64LegalI32)
- addRegisterClass(MVT::i32, &RISCV::GPRRegClass);
if (Subtarget.hasStdExtZfhmin())
addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
@@ -243,12 +237,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, XLenVT, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::BR_CC, MVT::i32, Expand);
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
setCondCodeAction(ISD::SETGT, XLenVT, Custom);
setCondCodeAction(ISD::SETGE, XLenVT, Expand);
@@ -259,15 +249,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setCondCodeAction(ISD::SETLE, XLenVT, Expand);
}
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::SETCC, MVT::i32, Promote);
-
setOperationAction({ISD::STACKSAVE, ISD::STACKRESTORE}, MVT::Other, Expand);
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction({ISD::VAARG, ISD::VACOPY, ISD::VAEND}, MVT::Other, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::VAARG, MVT::i32, Promote);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
@@ -280,33 +265,20 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.is64Bit()) {
setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
- if (!RV64LegalI32) {
- setOperationAction(ISD::LOAD, MVT::i32, Custom);
- setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL},
- MVT::i32, Custom);
- setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT},
- MVT::i32, Custom);
- if (!Subtarget.hasStdExtZbb())
- setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, MVT::i32, Custom);
- } else {
- setOperationAction(ISD::SSUBO, MVT::i32, Custom);
- if (Subtarget.hasStdExtZbb()) {
- setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, MVT::i32, Custom);
- setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Custom);
- }
- }
+ setOperationAction(ISD::LOAD, MVT::i32, Custom);
+ setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL},
+ MVT::i32, Custom);
+ setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT},
+ MVT::i32, Custom);
+ if (!Subtarget.hasStdExtZbb())
+ setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, MVT::i32, Custom);
setOperationAction(ISD::SADDO, MVT::i32, Custom);
}
if (!Subtarget.hasStdExtZmmul()) {
setOperationAction({ISD::MUL, ISD::MULHS, ISD::MULHU}, XLenVT, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::MUL, MVT::i32, Promote);
} else if (Subtarget.is64Bit()) {
setOperationAction(ISD::MUL, MVT::i128, Custom);
- if (!RV64LegalI32)
- setOperationAction(ISD::MUL, MVT::i32, Custom);
- else
- setOperationAction(ISD::SMULO, MVT::i32, Custom);
+ setOperationAction(ISD::MUL, MVT::i32, Custom);
} else {
setOperationAction(ISD::MUL, MVT::i64, Custom);
}
@@ -314,20 +286,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (!Subtarget.hasStdExtM()) {
setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM},
XLenVT, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, MVT::i32,
- Promote);
} else if (Subtarget.is64Bit()) {
- if (!RV64LegalI32)
- setOperationAction({ISD::SDIV, ISD::UDIV, ISD::UREM},
- {MVT::i8, MVT::i16, MVT::i32}, Custom);
- }
-
- if (RV64LegalI32 && Subtarget.is64Bit()) {
- setOperationAction({ISD::MULHS, ISD::MULHU}, MVT::i32, Expand);
- setOperationAction(
- {ISD::SDIVREM, ISD::UDIVREM, ISD::SMUL_LOHI, ISD::UMUL_LOHI}, MVT::i32,
- Expand);
+ setOperationAction({ISD::SDIV, ISD::UDIV, ISD::UREM},
+ {MVT::i8, MVT::i16, MVT::i32}, Custom);
}
setOperationAction(
@@ -338,7 +299,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
Custom);
if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) {
- if (!RV64LegalI32 && Subtarget.is64Bit())
+ if (Subtarget.is64Bit())
setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
} else if (Subtarget.hasVendorXTHeadBb()) {
if (Subtarget.is64Bit())
@@ -348,8 +309,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ROTL, XLenVT, Expand);
} else {
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Expand);
}
// With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
@@ -359,13 +318,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
Subtarget.hasVendorXTHeadBb())
? Legal
: Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::BSWAP, MVT::i32,
- (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb() ||
- Subtarget.hasVendorXTHeadBb())
- ? Promote
- : Expand);
-
if (Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit()) {
setOperationAction(ISD::BITREVERSE, XLenVT, Legal);
@@ -379,42 +331,24 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit())) {
setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT,
Legal);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32,
- Promote);
}
if (Subtarget.hasStdExtZbb() ||
(Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit())) {
- if (Subtarget.is64Bit()) {
- if (RV64LegalI32)
- setOperationAction(ISD::CTTZ, MVT::i32, Legal);
- else
- setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
- }
+ if (Subtarget.is64Bit())
+ setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
} else {
setOperationAction({ISD::CTTZ, ISD::CTPOP}, XLenVT, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction({ISD::CTTZ, ISD::CTPOP}, MVT::i32, Expand);
}
if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() ||
(Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit())) {
// We need the custom lowering to make sure that the resulting sequence
// for the 32bit case is efficient on 64bit targets.
- if (Subtarget.is64Bit()) {
- if (RV64LegalI32) {
- setOperationAction(ISD::CTLZ, MVT::i32,
- Subtarget.hasStdExtZbb() ? Legal : Promote);
- if (!Subtarget.hasStdExtZbb())
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
- } else
- setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
- }
+ if (Subtarget.is64Bit())
+ setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
} else {
setOperationAction(ISD::CTLZ, XLenVT, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::CTLZ, MVT::i32, Expand);
}
if (Subtarget.hasVendorXCValu() && !Subtarget.is64Bit()) {
@@ -422,15 +356,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
} else if (Subtarget.hasShortForwardBranchOpt()) {
// We can use PseudoCCSUB to implement ABS.
setOperationAction(ISD::ABS, XLenVT, Legal);
- } else if (!RV64LegalI32 && Subtarget.is64Bit()) {
+ } else if (Subtarget.is64Bit()) {
setOperationAction(ISD::ABS, MVT::i32, Custom);
}
- if (!Subtarget.hasVendorXTHeadCondMov()) {
+ if (!Subtarget.hasVendorXTHeadCondMov())
setOperationAction(ISD::SELECT, XLenVT, Custom);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::SELECT, MVT::i32, Promote);
- }
static const unsigned FPLegalNodeTypes[] = {
ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT,
@@ -614,11 +545,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
XLenVT, Legal);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT,
- ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
- MVT::i32, Legal);
-
setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
}
@@ -673,8 +599,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setBooleanVectorContents(ZeroOrOneBooleanContent);
setOperationAction(ISD::VSCALE, XLenVT, Custom);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::VSCALE, MVT::i32, Custom);
// RVV intrinsics may have illegal operands.
// We also need to custom legalize vmv.x.s.
@@ -1413,11 +1337,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
}
- if (Subtarget.hasStdExtA()) {
+ if (Subtarget.hasStdExtA())
setOperationAction(ISD::ATOMIC_LOAD_SUB, XLenVT, Expand);
- if (RV64LegalI32 && Subtarget.is64Bit())
- setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
- }
if (Subtarget.hasForcedAtomics()) {
// Force __sync libcalls to be emitted for atomic rmw/cas operations.
@@ -2340,9 +2261,6 @@ MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
MVT PartVT = TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
- if (RV64LegalI32 && Subtarget.is64Bit() && PartVT == MVT::i32)
- return MVT::i64;
-
return PartVT;
}
@@ -2364,12 +2282,6 @@ unsigned RISCVTargetLowering::getVectorTypeBreakdownForCallingConv(
unsigned NumRegs = TargetLowering::getVectorTypeBreakdownForCallingConv(
Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
- if (RV64LegalI32 && Subtarget.is64Bit() && IntermediateVT == MVT::i32)
- IntermediateVT = MVT::i64;
-
- if (RV64LegalI32 && Subtarget.is64Bit() && RegisterVT == MVT::i32)
- RegisterVT = MVT::i64;
-
return NumRegs;
}
@@ -5681,78 +5593,6 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
return Op;
}
-static SDValue lowerSADDSAT_SSUBSAT(SDValue Op, SelectionDAG &DAG) {
- assert(Op.getValueType() == MVT::i32 && RV64LegalI32 &&
- "Unexpected custom legalisation");
-
- // With Zbb, we can widen to i64 and smin/smax with INT32_MAX/MIN.
- bool IsAdd = Op.getOpcode() == ISD::SADDSAT;
- SDLoc DL(Op);
- SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(0));
- SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue Result =
- DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, DL, MVT::i64, LHS, RHS);
-
- APInt MinVal = APInt::getSignedMinValue(32).sext(64);
- APInt MaxVal = APInt::getSignedMaxValue(32).sext(64);
- SDValue SatMin = DAG.getConstant(MinVal, DL, MVT::i64);
- SDValue SatMax = DAG.getConstant(MaxVal, DL, MVT::i64);
- Result = DAG.getNode(ISD::SMIN, DL, MVT::i64, Result, SatMax);
- Result = DAG.getNode(ISD::SMAX, DL, MVT::i64, Result, SatMin);
- return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Result);
-}
-
-static SDValue lowerUADDSAT_USUBSAT(SDValue Op, SelectionDAG &DAG) {
- assert(Op.getValueType() == MVT::i32 && RV64LegalI32 &&
- "Unexpected custom legalisation");
-
- // With Zbb we can sign extend and let LegalizeDAG use minu/maxu. Using
- // sign extend allows overflow of the lower 32 bits to be detected on
- // the promoted size.
- SDLoc DL(Op);
- SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(0));
- SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue WideOp = DAG.getNode(Op.getOpcode(), DL, MVT::i64, LHS, RHS);
- return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, WideOp);
-}
-
-// Custom lower i32 SADDO/SSUBO with RV64LegalI32 so we take advantage of addw.
-static SDValue lowerSADDO_SSUBO(SDValue Op, SelectionDAG &DAG) {
- assert(Op.getValueType() == MVT::i32 && RV64LegalI32 &&
- "Unexpected custom legalisation");
- if (isa<ConstantSDNode>(Op.getOperand(1)))
- return SDValue();
-
- bool IsAdd = Op.getOpcode() == ISD::SADDO;
- SDLoc DL(Op);
- SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(0));
- SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue WideOp =
- DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, DL, MVT::i64, LHS, RHS);
- SDValue Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, WideOp);
- SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, WideOp,
- DAG.getValueType(MVT::i32));
- SDValue Ovf = DAG.getSetCC(DL, Op.getValue(1).getValueType(), WideOp, SExt,
- ISD::SETNE);
- return DAG.getMergeValues({Res, Ovf}, DL);
-}
-
-// Custom lower i32 SMULO with RV64LegalI32 so we take advantage of mulw.
-static SDValue lowerSMULO(SDValue Op, SelectionDAG &DAG) {
- assert(Op.getValueType() == MVT::i32 && RV64LegalI32 &&
- "Unexpected custom legalisation");
- SDLoc DL(Op);
- SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(0));
- SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
- SDValue Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
- SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, Mul,
- DAG.getValueType(MVT::i32));
- SDValue Ovf = DAG.getSetCC(DL, Op.getValue(1).getValueType(), Mul, SExt,
- ISD::SETNE);
- return DAG.getMergeValues({Res, Ovf}, DL);
-}
-
SDValue RISCVTargetLowering::LowerIS_FPCLASS(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
@@ -6267,11 +6107,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerFRAMEADDR(Op, DAG);
case ISD::RETURNADDR:
return lowerRETURNADDR(Op, DAG);
- case ISD::SADDO:
- case ISD::SSUBO:
- return lowerSADDO_SSUBO(Op, DAG);
- case ISD::SMULO:
- return lowerSMULO(Op, DAG);
case ISD::SHL_PARTS:
return lowerShiftLeftParts(Op, DAG);
case ISD::SRA_PARTS:
@@ -6710,7 +6545,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
RTLIB::getFPROUND(Op.getOperand(0).getValueType(), MVT::bf16);
SDValue Res =
makeLibCall(DAG, LC, MVT::f32, Op.getOperand(0), CallOptions, DL).first;
- if (Subtarget.is64Bit() && !RV64LegalI32)
+ if (Subtarget.is64Bit())
return DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Res);
return DAG.getBitcast(MVT::i32, Res);
}
@@ -6739,7 +6574,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
RTLIB::getFPROUND(Op.getOperand(0).getValueType(), MVT::f16);
SDValue Res =
makeLibCall(DAG, LC, MVT::f32, Op.getOperand(0), CallOptions, DL).first;
- if (Subtarget.is64Bit() && !RV64LegalI32)
+ if (Subtarget.is64Bit())
return DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Res);
return DAG.getBitcast(MVT::i32, Res);
}
@@ -7033,13 +6868,9 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerToScalableOp(Op, DAG);
case ISD::UADDSAT:
case ISD::USUBSAT:
- if (!Op.getValueType().isVector())
- return lowerUADDSAT_USUBSAT(Op, DAG);
return lowerToScalableOp(Op, DAG);
case ISD::SADDSAT:
case ISD::SSUBSAT:
- if (!Op.getValueType().isVector())
- return lowerSADDSAT_SSUBSAT(Op, DAG);
return lowerToScalableOp(Op, DAG);
case ISD::ABDS:
case ISD::ABDU: {
@@ -9098,13 +8929,6 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::riscv_sm3p1: Opc = RISCVISD::SM3P1; break;
}
- if (RV64LegalI32 && Subtarget.is64Bit() && Op.getValueType() == MVT::i32) {
- SDValue NewOp =
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp);
- return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res);
- }
-
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1));
}
case Intrinsic::riscv_sm4ks:
@@ -9112,16 +8936,6 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
unsigned Opc =
IntNo == Intrinsic::riscv_sm4ks ? RISCVISD::SM4KS : RISCVISD::SM4ED;
- if (RV64LegalI32 && Subtarget.is64Bit() && Op.getValueType() == MVT::i32) {
- SDValue NewOp0 =
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue NewOp1 =
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2));
- SDValue Res =
- DAG.getNode(Opc, DL, MVT::i64, NewOp0, NewOp1, Op.getOperand(3));
- return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res);
- }
-
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2),
Op.getOperand(3));
}
@@ -9131,63 +8945,21 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
IntNo == Intrinsic::riscv_zip ? RISCVISD::ZIP : RISCVISD::UNZIP;
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1));
}
- case Intrinsic::riscv_mopr: {
- if (RV64LegalI32 && Subtarget.is64Bit() && Op.getValueType() == MVT::i32) {
- SDValue NewOp =
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue Res = DAG.getNode(
- RISCVISD::MOPR, DL, MVT::i64, NewOp,
- DAG.getTargetConstant(Op.getConstantOperandVal(2), DL, MVT::i64));
- return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res);
- }
+ case Intrinsic::riscv_mopr:
return DAG.getNode(RISCVISD::MOPR, DL, XLenVT, Op.getOperand(1),
Op.getOperand(2));
- }
case Intrinsic::riscv_moprr: {
- if (RV64LegalI32 && Subtarget.is64Bit() && Op.getValueType() == MVT::i32) {
- SDValue NewOp0 =
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue NewOp1 =
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2));
- SDValue Res = DAG.getNode(
- RISCVISD::MOPRR, DL, MVT::i64, NewOp0, NewOp1,
- DAG.getTargetConstant(Op.getConstantOperandVal(3), DL, MVT::i64));
- return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res);
- }
return DAG.getNode(RISCVISD::MOPRR, DL, XLenVT, Op.getOperand(1),
Op.getOperand(2), Op.getOperand(3));
}
case Intrinsic::riscv_clmul:
- if (RV64LegalI32 && Subtarget.is64Bit() && Op.getValueType() == MVT::i32) {
- SDValue NewOp0 =
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(1));
- SDValue NewOp1 =
- DAG.getNode(ISD::ANY_EXTEND, D...
[truncated]
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
topperc
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Based on experience with SelectionDAG and experimental-rv64-legal-i32, I don't believe making s32 a legal type is viable without introducing an invariant that s32 values are always sign extended like Mips64 does. Mips64 does this with a separate 32-bit register class. experimental-rv64-legal-i32 is proposed for removal in #llvm#102509. This patch is part of a series to remove s32 support so we can remove the isel patterns that SelectionDAG is no longer using. To restore code quality, we will need to add custom W nodes like SelectionDAG.
s-barannikov
reviewed
Aug 8, 2024
wangpc-pp
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Aug 9, 2024
kutemeikito
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Aug 10, 2024
* 'main' of https://github.com/llvm/llvm-project: (700 commits) [SandboxIR][NFC] SingleLLVMInstructionImpl class (llvm#102687) [ThinLTO]Clean up 'import-assume-unique-local' flag. (llvm#102424) [nsan] Make #include more conventional [SandboxIR][NFC] Use Tracker.emplaceIfTracking() [libc] Moved range_reduction_double ifdef statement (llvm#102659) [libc] Fix CFP long double and add tests (llvm#102660) [TargetLowering] Handle vector types in expandFixedPointMul (llvm#102635) [compiler-rt][NFC] Replace environment variable with %t (llvm#102197) [UnitTests] Convert a test to use opaque pointers (llvm#102668) [CodeGen][NFCI] Don't re-implement parts of ASTContext::getIntWidth (llvm#101765) [SandboxIR] Clean up tracking code with the help of emplaceIfTracking() (llvm#102406) [mlir][bazel] remove extra blanks in mlir-tblgen test [NVPTX][NFC] Update tests to use bfloat type (llvm#101493) [mlir] Add support for parsing nested PassPipelineOptions (llvm#101118) [mlir][bazel] add missing td dependency in mlir-tblgen test [flang][cuda] Fix lib dependency [libc] Clean up remaining use of *_WIDTH macros in printf (llvm#102679) [flang][cuda] Convert cuf.alloc for box to fir.alloca in device context (llvm#102662) [SandboxIR] Implement the InsertElementInst class (llvm#102404) [libc] Fix use of cpp::numeric_limits<...>::digits (llvm#102674) [mlir][ODS] Verify type constraints in Types and Attributes (llvm#102326) [LTO] enable `ObjCARCContractPass` only on optimized build (llvm#101114) [mlir][ODS] Consistent `cppType` / `cppClassName` usage (llvm#102657) [lldb] Move definition of SBSaveCoreOptions dtor out of header (llvm#102539) [libc] Use cpp::numeric_limits in preference to C23 <limits.h> macros (llvm#102665) [clang] Implement -fptrauth-auth-traps. (llvm#102417) [LLVM][rtsan] rtsan transform to preserve CFGAnalyses (llvm#102651) Revert "[AMDGPU] Move `AMDGPUAttributorPass` to full LTO post link stage (llvm#102086)" [RISCV][GISel] Add missing tests for G_CTLZ/CTTZ instruction selection. NFC Return available function types for BindingDecls. (llvm#102196) [clang] Wire -fptrauth-returns to "ptrauth-returns" fn attribute. (llvm#102416) [RISCV] Remove riscv-experimental-rv64-legal-i32. (llvm#102509) [RISCV] Move PseudoVSET(I)VLI expansion to use PseudoInstExpansion. (llvm#102496) [NVPTX] support switch statement with brx.idx (reland) (llvm#102550) [libc][newhdrgen]sorted function names in yaml (llvm#102544) [GlobalIsel] Combine G_ADD and G_SUB with constants (llvm#97771) Suppress spurious warnings due to R_RISCV_SET_ULEB128 [scudo] Separated committed and decommitted entries. (llvm#101409) [MIPS] Fix missing ANDI optimization (llvm#97689) [Clang] Add env var for nvptx-arch/amdgpu-arch timeout (llvm#102521) [asan] Switch allocator to dynamic base address (llvm#98511) [AMDGPU] Move `AMDGPUAttributorPass` to full LTO post link stage (llvm#102086) [libc][math][c23] Add fadd{l,f128} C23 math functions (llvm#102531) [mlir][bazel] revert bazel rule change for DLTITransformOps [msan] Support vst{2,3,4}_lane instructions (llvm#101215) Revert "[MLIR][DLTI][Transform] Introduce transform.dlti.query (llvm#101561)" [X86] pr57673.ll - generate MIR test checks [mlir][vector][test] Split tests from vector-transfer-flatten.mlir (llvm#102584) [mlir][bazel] add bazel rule for DLTITransformOps OpenMPOpt: Remove dead include [IR] Add method to GlobalVariable to change type of initializer. (llvm#102553) [flang][cuda] Force default allocator in device code (llvm#102238) [llvm] Construct SmallVector<SDValue> with ArrayRef (NFC) (llvm#102578) [MLIR][DLTI][Transform] Introduce transform.dlti.query (llvm#101561) [AMDGPU][AsmParser][NFC] Remove a misleading comment. (llvm#102604) [Arm][AArch64][Clang] Respect function's branch protection attributes. (llvm#101978) [mlir] Verifier: steal bit to track seen instead of set. (llvm#102626) [Clang] Fix Handling of Init Capture with Parameter Packs in LambdaScopeForCallOperatorInstantiationRAII (llvm#100766) [X86] Convert truncsat clamping patterns to use SDPatternMatch. NFC. [gn] Give two scripts argparse.RawDescriptionHelpFormatter [bazel] Add missing dep for the SPIRVToLLVM target [Clang] Simplify specifying passes via -Xoffload-linker (llvm#102483) [bazel] Port for d45de80 [SelectionDAG] Use unaligned store/load to move AVX registers onto stack for `insertelement` (llvm#82130) [Clang][OMPX] Add the code generation for multi-dim `num_teams` (llvm#101407) [ARM] Regenerate big-endian-vmov.ll. NFC [AMDGPU][AsmParser][NFCI] All NamedIntOperands to be of the i32 type. (llvm#102616) [libc][math][c23] Add totalorderl function. (llvm#102564) [mlir][spirv] Support `memref` in `convert-to-spirv` pass (llvm#102534) [MLIR][GPU-LLVM] Convert `gpu.func` to `llvm.func` (llvm#101664) Fix a unit test input file (llvm#102567) [llvm-readobj][COFF] Dump hybrid objects for ARM64X files. (llvm#102245) AMDGPU/NewPM: Port SIFixSGPRCopies to new pass manager (llvm#102614) [MemoryBuiltins] Simplify getCalledFunction() helper (NFC) [AArch64] Add invalid 1 x vscale costs for reductions and reduction-operations. (llvm#102105) [MemoryBuiltins] Handle allocator attributes on call-site LSV/test/AArch64: add missing lit.local.cfg; fix build (llvm#102607) Revert "Enable logf128 constant folding for hosts with 128bit floats (llvm#96287)" [RISCV] Add Syntacore SCR5 RV32/64 processors definition (llvm#102285) [InstCombine] Remove unnecessary RUN line from test (NFC) [flang][OpenMP] Handle multiple ranges in `num_teams` clause (llvm#102535) [mlir][vector] Add tests for scalable vectors in one-shot-bufferize.mlir (llvm#102361) [mlir][vector] Disable `vector.matrix_multiply` for scalable vectors (llvm#102573) [clang] Implement CWG2627 Bit-fields and narrowing conversions (llvm#78112) [NFC] Use references to avoid copying (llvm#99863) Revert "[mlir][ArmSME] Pattern to swap shape_cast(tranpose) with transpose(shape_cast) (llvm#100731)" (llvm#102457) [IRBuilder] Generate nuw GEPs for struct member accesses (llvm#99538) [bazel] Port for 9b06e25 [CodeGen][NewPM] Improve start/stop pass error message CodeGenPassBuilder (llvm#102591) [AArch64] Implement TRBMPAM_EL1 system register (llvm#102485) [InstCombine] Fixing wrong select folding in vectors with undef elements (llvm#102244) [AArch64] Sink operands to fmuladd. (llvm#102297) LSV: document hang reported in llvm#37865 (llvm#102479) Enable logf128 constant folding for hosts with 128bit floats (llvm#96287) [RISCV][clang] Remove bfloat base type in non-zvfbfmin vcreate (llvm#102146) [RISCV][clang] Add missing `zvfbfmin` to `vget_v` intrinsic (llvm#102149) [mlir][vector] Add mask elimination transform (llvm#99314) [Clang][Interp] Fix display of syntactically-invalid note for member function calls (llvm#102170) [bazel] Port for 3fffa6d [DebugInfo][RemoveDIs] Use iterator-inserters in clang (llvm#102006) ... Signed-off-by: Edwiin Kusuma Jaya <kutemeikito0905@gmail.com>
topperc
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Based on experience with SelectionDAG and experimental-rv64-legal-i32, I don't believe making s32 a legal type is viable without introducing an invariant that s32 values are always sign extended like Mips64 does. Mips64 does this with a separate 32-bit register class. `experimental-rv64-legal-i32` was removed in ##102509. This patch is part of a series to remove s32 support so we can remove the isel patterns that SelectionDAG is no longer using. To restore code quality, we will need to add custom W nodes like SelectionDAG.
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This has received no development work in a while and is slowly bit rotting as new extensions are added.
At the moment, I don't think this is viable without adding a new invariant that 32 bit values are always in sign extended form like Mips64 does. We are very dependent on computeKnownBits and ComputeNumSignBits in SelectionDAG to remove sign extends created for ABI reasons. If we can't propagate sign bit information through 64-bit values in SelectionDAG, we can't effectively clean up those extends.