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[mlir][llvm] Add llvm.intr.exp10 operation
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FantasqueX committed Mar 1, 2025
1 parent 0751418 commit 90ebe2e
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Showing 3 changed files with 21 additions and 0 deletions.
1 change: 1 addition & 0 deletions mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,7 @@ def LLVM_IsFPClass : LLVM_OneResultIntrOp<"is.fpclass", [], [0], [Pure],
def LLVM_CopySignOp : LLVM_BinarySameArgsIntrOpF<"copysign">;
def LLVM_ExpOp : LLVM_UnaryIntrOpF<"exp">;
def LLVM_Exp2Op : LLVM_UnaryIntrOpF<"exp2">;
def LLVM_Exp10Op : LLVM_UnaryIntrOpF<"exp10">;
def LLVM_FAbsOp : LLVM_UnaryIntrOpF<"fabs">;
def LLVM_FCeilOp : LLVM_UnaryIntrOpF<"ceil">;
def LLVM_FFloorOp : LLVM_UnaryIntrOpF<"floor">;
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11 changes: 11 additions & 0 deletions mlir/test/Target/LLVMIR/Import/intrinsic.ll
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Expand Up @@ -42,6 +42,15 @@ define void @exp2_test(float %0, <8 x float> %1) {
ret void
}

; CHECK-LABEL: llvm.func @exp10_test
define void @exp10_test(float %0, <8 x float> %1) {
; CHECK: llvm.intr.exp10(%{{.*}}) : (f32) -> f32
%3 = call float @llvm.exp10.f32(float %0)
; CHECK: llvm.intr.exp10(%{{.*}}) : (vector<8xf32>) -> vector<8xf32>
%4 = call <8 x float> @llvm.exp10.v8f32(<8 x float> %1)
ret void
}

; CHECK-LABEL: llvm.func @log_test
define void @log_test(float %0, <8 x float> %1) {
; CHECK: llvm.intr.log(%{{.*}}) : (f32) -> f32
Expand Down Expand Up @@ -1022,6 +1031,8 @@ declare float @llvm.exp.f32(float)
declare <8 x float> @llvm.exp.v8f32(<8 x float>)
declare float @llvm.exp2.f32(float)
declare <8 x float> @llvm.exp2.v8f32(<8 x float>)
declare float @llvm.exp10.f32(float)
declare <8 x float> @llvm.exp10.v8f32(<8 x float>)
declare float @llvm.log.f32(float)
declare <8 x float> @llvm.log.v8f32(<8 x float>)
declare float @llvm.log10.f32(float)
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9 changes: 9 additions & 0 deletions mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
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Expand Up @@ -40,6 +40,15 @@ llvm.func @exp2_test(%arg0: f32, %arg1: vector<8xf32>) {
llvm.return
}

// CHECK-LABEL: @exp10_test
llvm.func @exp10_test(%arg0: f32, %arg1: vector<8xf32>) {
// CHECK: call float @llvm.exp10.f32
"llvm.intr.exp10"(%arg0) : (f32) -> f32
// CHECK: call <8 x float> @llvm.exp10.v8f32
"llvm.intr.exp10"(%arg1) : (vector<8xf32>) -> vector<8xf32>
llvm.return
}

// CHECK-LABEL: @log_test
llvm.func @log_test(%arg0: f32, %arg1: vector<8xf32>) {
// CHECK: call float @llvm.log.f32
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